<bl0x>
I thought there was a way to do this in Amaranth, but perhaps not: I'd like to copy a single bit from one signal "src = Signal(8)" to a 1-bit signal "dst = Signal()". Which bit to select for copy depends on yet another signal "selected_bit = Signal(3)". IMO this code should do the copy: "m.d.sync += dst.eq(src[selected_bit])". However, Amaranth complains with "TypeError: Cannot index value with (sig selected_bit)". How does one get around
<bl0x>
this usually?
<tpw_rules>
a mux is how i would do it
<bl0x>
Hm, 8 way mux then? I could also shift src by 1 every time.
<bl0x>
And use a constant index. Where does this limitation come from?
<bl0x>
There seems to be no problem indexing Array elements with a variable signal.
<d1b2>
<Olivier Galibert> because it's memory?
<d1b2>
<Olivier Galibert> I mean the arrays
<d1b2>
<Olivier Galibert> can you variable-shift?
<d1b2>
<Olivier Galibert> (I'm not sure whether amaranth allows it)
<bl0x>
Ah, I don't need random access to the bits. I just need one after the other.
<d1b2>
<Olivier Galibert> Ah, when I did that for serial I used a 9-bt shift register with a final '1' as a sentinel
<d1b2>
<Olivier Galibert> doesn't really add more resources than what a mux would
<bl0x>
Ok, I'll check it out. Verilog seems to have no problem with variable indexing though.
<bl0x>
Thanks ppl
<d1b2>
<OmniTechnoMancer> bl0x: you desire bit_select
<bl0x>
Yeah, I tried that too and then got a cryptic error message. About it not being a statement.
<d1b2>
<OmniTechnoMancer> can you show error?
<d1b2>
<OmniTechnoMancer> And like how you tried to use it?
<bl0x>
Oh, oops. It was a cryptic message because the line in question is fine, and it found another error further down. I failed to realize. Sorry, I'll go to my room now.
<d1b2>
<OmniTechnoMancer> Ah all good
<bl0x>
I did "dst.eq(src.bit_select(selected_bit, 1))", and I think that is the way to do it?
<d1b2>
<OmniTechnoMancer> bit_select is how you do indexing if you need the index to be an HDL signal
<d1b2>
<OmniTechnoMancer> Verilog basically does not distinguish the cases syntactically AFAIK
<d1b2>
<Olivier Galibert> but python probably gets cranky if you want slices to work too
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<whitequark>
hi everyone, it is time for our scheduled weekly meeting