<d1b2>
<dave berkeley> I'd like to be able to add bitslices of signals as named traces for a VCD dump in pysim.py I have a payload Signal. I'd like to be able to generate a named trace for slices of that payload. Is this something that the replacement for Record will be able to do?
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<d1b2>
<josuah_dem> So, you ask things that people would consider trivial, I conclude you are asking in the right place!
<josuah>
@VA3TEC-Mikek-14362: I think lawrie played with amaranth since early on, these projects might have been built for an earlier version of Amaranth
<d1b2>
<VA3TEC-Mikek-14362> HaHa ๐ Thanks! Yes, So Good news I figured it out! I was putting in the wrong io standard, and voltage setting. it was from Lawrie's project. I was able to get past that part ! Now it's dying on the pin names, The code I am using using is adding a "" in the pin name, and Quartus does not like that. I think it's a python finger problem. Still going through it. I am still learning python, :). Other good news I finally
<d1b2>
broke down I bought the Siglent SDS2000x Plus. with the logic probes. HAPPY happy Joy joy! Now just to have to get some twittly bits on the screen!! ๐ Thanks Josuah! Appreciate your helpful comments! ๐
<josuah>
a cheap logic analyzer is also convenient and some cheap clones of a discontinuited do a good job for very low speeds, such as I2C/SPI/UART/...