<josuah>
which answers the question \o/ it takes the greater out of the two shapes as a destination signal
<d1b2>
<Olivier Galibert> yay!
<d1b2>
<Olivier Galibert> but that doesn't tell whether it zero-fills the extra bits or actually copies b
<d1b2>
<Olivier Galibert> because the answer is way less obvious if shape(a) = unsigned(4) and shape(b) = unsigned(3)
<d1b2>
<Olivier Galibert> you know that shape(a&b) = unsigned(4) but that's it
<d1b2>
<Olivier Galibert> (sorry, been looking at a lot of quantum mechanics math lately, I'm in a formal mood)
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<PatD>
Bonjour! I haven't done formal verif in Amaranth since ye olde days of nMigen, and as I was coding along I updated yosys hq's oss-cad-suite ('cause I'm lazy and it has everything I need in a bundle, including amaranth). Short story, newer amaranth in there has a deprecation warning "instead of using `Past`, create a register explicitly" and
<PatD>
there's nothing I can find in docs or git logs that gives me a clue what is really meant by this.
<PatD>
So my questions are:
<PatD>
* is there an example of this new approach somewhere?
<PatD>
* do you need assist in documenting this further?
<PatD>
Ok, guessing I should come back on mondays... I'm assuming this means manually creating a FIFO and checking that, or somesuch (?). If a maintainer-type person should happen to see this, and you're interested in documenting/tutorial type stuff, I'm not Baruch-level but I do create some content and my last 2 vids were amaranth-related (starts with
<PatD>
https://www.youtube.com/watch?v=h9_4jBKhs9k ) so if you're interested in docs or specific tutorial/walk-through type stuff, get in touch through there and lemme know! Gotta go, cheers!
<josuah>
Olivier Galibert: my impression is it that it zero fills, but that is only guessed from the practice of implicitly zero-filling Signals at reset Amaranth has
<josuah>
Bonjour PatD, voyons-voir...
<josuah>
PatD: what I understand with using a register explicitly instead of using past (like $past() would have been in Verilog/SystemVerilog) would be:
<josuah>
for a combinational signal (wire in Verilog) named 'something_d', adding a synchronous signal named 'something_q' (register in Verilog) that gets updated at every clock with the value of 'something_d'
<josuah>
then at any given time, 'something_q' contains the value that 'something_d' had the previous clock
<josuah>
maybe something like that: m.d.sync += something_q.eq(something_d)
<josuah>
for supporting arbitrary amount of $past() values, some shift register could be used
<josuah>
that is some catchy video
<PatD>
Hah, thanks, and thanks for the answer. So yeah, am working on a bit of frequency counting so I'll try to implement that using a (relatively) gigantic SyncFIFO or something.
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<PatD>
Actually, maybe a Memory is a more appropriate tool...
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<PatD>
Yeah, no... the sync, the mem, all that stuff is overly convoluted... Best I could come up with is something like
<PatD>
outputs = Signal(100)
<PatD>
inputs = Signal(100)
<PatD>
count = Signal(range(100))
<PatD>
for i in range(100):
<PatD>
with m.If(count == i):
<PatD>
m.d.sync += [
<PatD>
outputs[i].eq(edgedetect.output),
<PatD>
inputs[i].eq(edgedetect.input)
<PatD>
]
<PatD>
m.d.sync += count.eq(count + 1)
<PatD>
to keep track of the history rather than use Past, and it seems ridiculous. So will wait until the meet or some assist on how we're supposed to replace Past now that we're in Future.
<crzwdjk>
PatD: you can use inputs.bit_select(count, 1) instead of your loop, for one thing, so that makes things a bit simpler.
<PatD>
Hi crzwdjk, thanks for the tip--didn't know this accessor. My main issue however is the history tracking itself--I'm assuming it cannot be that I have to implement this in every test I perform, but I can't locate any docs on what we're supposed to use instead of Past().
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<whitequark>
a register
<whitequark>
or several registers
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<cr1901>
To be explicit, Assert and Assume aren't going away (for now), just Past?
<cr1901>
Btw, I've read that for loop in that sample code several times, what is it intended to do?
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<PatD>
Hi, sorry whitequark, I go booted out then it didn't refresh the message I'd missed when it let me back in. A register... could you point me to a place in the tests where this is used?
<PatD>
To view the past, I mean, say 10 ticks ago for instance.\
<PatD>
All right, well for anyone that might find this of use, I've implemented a basic snapshot system to track signal of interest
<PatD>
lol, just saw the log of my recent posts--libera chops it all up in very interesting ways. So, I'll push this to my fork if there's no better official way. a+
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<whitequark>
Assert and Assume are here to stay, yes