azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<pie___> are there any cpu archs where you can directly address bits instead of shifting around and such?
<pie___> I imagine some of the fancy vectorized operations might actually be suitable for such but I don't know my way around that
<pie___> I'm just wondering about this, no specific applications in mind
<Flea86> pie___: 8051? Cortex M0+? :> *runs away*
<Flea86> Seriously tho, those two archs have bit-addressable memory and instructions to access that space
<Flea86> Dunno about microprocessors tho.. 68k is the closest arch I can think of that could do bit handling.
<Flea86> sorta
<Flea86> Aha, I was thinking of the 68020!
<pie___> thanks!
<pie___> Flea86: do you know what this is called? Searching cortex m0 bit addressing doesnt really seem to yield too relevant results
<Flea86> pie___: On Cortex m0, ARM calls it 'bit-banding;
<Flea86> *bit-banding
<pie___> apparently its bit banding but its from m3 up https://atadiat.com/en/e-bit-banding-explained-a-feature-of-arm-cortex-m3/
<pie___> aha
<Flea86> Pretty sure M0+ has it too
<Flea86> if not M0
<pie___> hm well ok maybe
<pie___> also apparently some sort of memory mapping or somesuch may be involved, but ill have to read more about it later
<Flea86> Ok
<Flea86> You are right though, M3 definitely has it
<pie___> well, Im just going off what I skimmed from the above article
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<Flea86> pie___: And I am going on the bit rot that is my brain :D
<Flea86> Ok, seems some, though not all, M0+ parts have bit-banding as standard.
<Flea86> Makes sense.
<Flea86> (well not really :-)
<Flea86> All 8051 variants have so-called 'bit-addressible memory' as standard.
<Flea86> Ask me how I know that one :>
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<somlo> Flea86: an update, since we talked about it the other day: the pin mapping on the new STLV7325 board version has indeed changed. The seller sent me enough to get the UART and DDR3 working to the point I can boot a litex vexriscv system at 100MHz and pass the memory test :)
<somlo> still no idea what the pins are for ethernet, sata, or the sdcard
<somlo> but I've been promised schematics within a week or so, therefore I'm optimistic
<Flea86> smolo: Thanks for your update. Least he could do is give you an updated pin declaration file for the FPGA, but yeah if it's a new board I think you'll get related schematics soon enough.
<Flea86> smolo: Should be able to crank that core up to 200MHz now :)