azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<Forty-Bot>
it would be nice to just have a (* global *) attribute
<tnt>
Forty-Bot: what do yo mean when the generating module uses that signal ? I usually have a "crg" module that generates all the clocking and reset and those details are isolated in there.
<Forty-Bot>
sometimes the reset is programmatic
<Forty-Bot>
but maybe that is the way to go...
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<pie_>
apparently tinytapeout3 was announced recently 3 weeks to submission, does this mean turnaround is kind of fast now? I dont immediately see the manufacturing timeline https://tinytapeout.com/
<pie_>
ah, deeper in the faq TT03 - will be submitted to ChipIgnite 2304C - wafers September 2023, deliver should be around a month after.
<pie_>
ok so not that fast
<pie_>
6 months is kind of a lot. oh well, too bad I guess. I don't have time to get up and running in 3 weeks.
<pie_>
(I hope I will be able to use a higher HDL but that of course just means I need to learn that _and_ the lower HDLs they compile to)
<gurki_>
"higher hdls" usually lead to more, not fewer problems :P
<somlo>
there's a strong opinion current against verilog and c (in hdl and software "circles", respectively). very eloquent and articulate "activist" types loudly proclaiming they're garbage :)
<somlo>
I don't have the debate-club skills to argue against that current, but IMHO keeping it simple has its definite advantages :D
<pie_>
somlo: thats true
<pie_>
are verilog and vhdl simple though:
<pie_>
s/?/
<pie_>
doesnt one of them have the problem that noone ever knows which subsets of the language synthesize and which simulate
<pie_>
either way you end up shooting yourself in the foot one way or another?
<somlo>
verilog (the synthesizable portion, at least) is the "c" of HDLs (I don't know vhdl, so I have no useful opinion there)
<somlo>
pie_: https://en.wikiquote.org/wiki/Brian_Kernighan -- to paraphrase, "it's twice as hard to debug code than it is to write it; so, if you write code as cleverly as you can, you're by definition too dumb to debug it" :)
<pie_>
hehe
<pie_>
even if you debate skills arent great you seem to have a quote for everything ;p
<gurki_>
vhdl and verilog are fine; id stay away from any form of high level synthesis for now (or forever :p)
<gurki_>
verilog kinda needs a good linter since its not forcing you to be precise like vhdl
<gurki_>
on the other hand that makes verilog way easier to deal with for mixed signal designs
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<Forty-Bot>
vhdl is the ada of HDLs...
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