20:46 <pie_> so with all these opportunities for small scale silicon manufacturing these days, I'm fantasizing about doing a cpu for my bachelors thesis but I doubt I could find a local thesis advisor that could handle it and I would probably have to learn a LOT of stuff (I'm doing a crappy/medium backwater CS degree)

20:51 <pie_> is there a list of these somewhere? I can't actually remember any names

20:52 <pie_> i.e. these projects that provide asic manufacturing for individuals

21:17 <somlo_> pie_: I'd recommend checking with your ECE department (the separation between "software" / CS and "hardware" / ECE might be different at your school, so ymmv)

21:18 <somlo_> where I work (and get to take free courses as an employee) they have an entire track dedicated to building Analog and Digital VLSI circuits

21:19 <somlo_> they start in sophomore year (200) with resistors, inductances, capacitors, and op amps in general, then 300 with a deeper dive into [c]mos and their behavior in actual silicon (using cadence and a 45nm "mock" process node)

21:19 <somlo_> then a deeper dive into digital in 400, followed by an actual tape-out course

21:20 <somlo_> guess where I'm going with this is that there's a lot of moving parts, and ECE is where they teach that in school. You might be able to pick up enough on your own to play around with one of the "free" PDKs (was it "skywater", maybe?)

21:21 <somlo_> but I, for one, won't go near any of that before I take some courses where someone else teaches me what to even look for :)

21:21 <somlo_> just my $0.02 from the peanut gallery :D

21:32 <pie_> (i found the openmdk stuff meanwhile, and i think tinytapeout is also on top of that?)

21:35 <pie_> yeah this seems hard :P <somlo_> but I, for one, won't go near any of that before I take some courses where someone else teaches me what to even look for :)

21:35 <pie_> there is a lot of great univerity courses on youtube but there also seems to be a lot of holes

21:35 <pie_> and its not the easiest thing to put together your own curriculum

21:36 <pie_> Im going to send a couple emails around but I dont think our EE people go in this direction, I know there is some FPGA stuff but of course thats just a stepping stone

21:37 <pie_> I have a bit of physics background and I'm OK at math, but yeah, still very "fantasy" stage currently :P

21:46 <pie_> somlo: thanks for the input!

22:43 <somlo> pie_: you're right, there *is* a lot of stuff out there, but, as you pointed out, the process of picking what to pay attention to is in itself difficult, particularly if you don't already know what you're looking for (bit of a catch-22)

22:43 <somlo> good luck with your thesis either way! :)

22:49 <pie_> I have way too much to do this semester but the time to start preparing is now

22:50 <pie_> if for no reason other than who knows when a tapeout will happen. I think tinytapeout has one listed for november

22:51 <pie_> I have two semesters left besides this one _if_ I go with the planned curriculum

22:56 <pie_> my best bet is probably trying to grind through some textbooks if nothing else. There Analog and Digital Electronic Circuits seems like a good intro textbook, and https://www.zerotoasiccourse.com/resources/ lists "CMOS VLSI Design by Weste & Harris: Expensive but excellent."

22:57 <pie_> not sure how much I need to bridge there,

22:57 <pie_> looking at other university syllabi should at least help a bit, somlo can you maybe mention where you are?

22:58 <pie_> and then beyond that I expect learning and maybe getting access to tooling will be the other big thing

22:58 <pie_> (so three big parts? theory, practical stuff, and actually doing the thing)

23:00 <pie_> doing anything analog would probably be too hard; I imagine device physics is kind of nuts. - but Id get an excuse to review some electrodynamics at least. solid state physics is ???. I sadly left my physics degree before I got to that part :p

23:02 <gurki> pie_: i highly recommend that weste & harria book

23:03 <pie_> thanks! It does look good

23:03 <gurki> that got me started into the asic world :)

23:03 <gurki> its a tough read though

23:04 <pie_> I'm not the brightest tool in the shed but we will see.

23:04 <gurki> analog isnt that hard if you restrict yourself to a few parts; its gets out of hand quickly though

23:05 <pie_> accidentally the everything :)

23:05 <gurki> the well and guardring stuff will keep your brain occupied for a while though

23:05 <pie_> for starters I'll probably be happy if I can get an inverter out of the tooling haha

23:05 <pie_> mm

23:06 <gurki> thats a good start :)

23:07 <gurki> however, if your goal is a cpu going for pure digital and hdl might make more sense

23:08 <gurki> bonus points since you can just synthesize it to an fpga in case you dont find a way to tape it out

23:08 <pie_> heh

23:08 <gurki> doesnt quite work that way with analog

23:08 <pie_> well, I mean, it's still an inverter whether I draw it in the layers or its spit out as a gate template thingy :pp

23:09 <gurki> you still need an actual pdk and tools ;)

23:09 <pie_> right

23:09 <gurki> if its hdl you dont have to care about the underlying process for quite a while

23:10 <gurki> you need to think about stuff like sram/bram once you make the call regarding fpga/asic at some point

23:10 <pie_> for the hdl side itd probably be good to fpga it as an intermediate step anyway?

23:11 <gurki> you cannot easily port more sophisticated designs

23:11 <gurki> intel wrote a nice paper, let me find it

23:11 <gurki> https://dl.acm.org/doi/abs/10.1145/1508128.1508160

23:11 <gurki> should be of interest to you :)

23:12 <pie_> on that note, is it possible to simulate physical layout in fpga layout? does that even make sense? i imagine the fpga device is sufficiently different from the asic; iirc fpgas are usually on the most advanced process node and e.g. skywater is 130nm

23:12 <gurki> you can typically synthesize easier stuff to fpgas, that stops working at some point

23:12 <gurki> i dont get that question

23:12 <pie_> or does that not even matter really and the design tooling should handle all the propagation calculations properly anyway

23:13 <pie_> *simulate asic layout

23:13 <gurki> yes you can extract a post-layout netlist and simulate that, including parasitics

23:13 <pie_> can I pack stuff into an fpga in a way similar to how it would be laid out on the asic and get useful information out of that?

23:13 <gurki> not exactly fast, but feasible

23:13 <pie_> what i meant ^

23:13 <gurki> no you cant

23:14 <pie_> well, screwed up the indentation there but whatever

23:14 <pie_> ok

23:14 <pie_> (I understand that fpgas have some kind of basic blocks plus interconnect or something like that)

23:14 <gurki> the fpga has a quite specific set of configurable logic blocks and muxes

23:14 <gurki> if its a fancy one you also get dsp slices and whatnot

23:14 <gurki> for asics you will typically use a standard cell grid, but apart from that you can just directly place optimized gates wherever it suits you

23:15 <pie_> meanwhile, thanks for the linl

23:15 <pie_> link

23:15 <gurki> np :)

23:15 <pie_> (when I said "as a gate template thingy" I meant standard cell but forgot the term)

23:16 <gurki> if theres a class at your university you should take it, if only to get to play with the "usual" asic tools

23:16 <gurki> its hard to impossible to get hands on these unless working in that field

23:17 <pie_> I know there is some xilinx fpga stuff but no idea about asic.

23:17 <pie_> I find it unlikely, but I'll be asking around.

23:17 <pie_> they almost certainly have stuff in Budapest, but I don't know if we have any tight enough connections there.

23:18 <pie_> my backup plan is to ask nicely here :pp

23:18 <gurki> there are options depending on how badly you want it

23:19 <gurki> theres a lot of small fabs/design companies willing to have external ppl write their thesis at their place in some kind of collaboration

23:20 <gurki> but generally speaking ppl wont grant access to somebody "asking nicely" :P

23:20 <pie_> it's a start though ;p

23:20 <gurki> sure :)

23:21 <pie_> if for no other reason than someone like gurki giving suggestions on how to go from there , e.g. the above

23:21 <pie_> Ill probably start asking around when I can demonstrate that Im not _completely_ useless in the topic

23:22 <pie_> modulo university opportunities

23:22 <pie_> whew, I'm getting tired just thinking about involved this is...

23:23 <gurki> well if you want to get into digital asics then having a good grasp of hdl is a good start :)

23:34 <pie_> whats a reasonable cpu clock speed that could be acheived on openmpw?

23:36 <gurki> i havent even looked into the skywater pdk so i cannot give a reasonable answer to that

23:36 <gurki> however, you will not compete with anything recent on 130nm

23:37 <pie_> yeah I didn't expect you to know, but IDK, order of magnitude tens - hundreds of MHz? GHz?

23:38 <gurki> my random guess would be tens of MHz, but dont quote me on that

23:38 <gurki> mb hundred if you spend a bit of effort

23:38 <pie_> totally random article has a listing of 40MHz

23:39 <gurki> they also seem to force you to use the openroad flow, i dont know how well that synthesis tool can optimize

23:39 <gurki> eh. openlane*

23:39 <pie_> trying to figure out how to copy the url...

23:40 <gurki> i guess i should have a look at how much effort id need to put into porting a random design just to see what kinda thing id get out of it

23:41 <pie_> https://www.techrxiv.org/ndownloader/files/38633663/1 An Open-Source ASIC Implementation of RISC-V based SoC

23:41 <pie_> lists 40 MHz (didnt read any deeper)

23:49 <pie_> "mpw-7 submission deadline is september 12"

23:53 <pie_> If I could make a shitty cpu that actually works, then I could write a shitty compiler for it, and a shitty operating system, and a shitty network stack :3

23:54 <pie_> the PCI bus isnt that hard right? xD

23:58 <pie_> ok no pci is actually really fast

23:59 <gurki> id start with an uart interface or something :P

23:59 <pie_> haha, right