00:10 <|{ame> hello, why does this

00:10 <|{ame> module laspi(clk,leds);

00:10 <|{ame>    input clk;

00:10 <|{ame>    output [7:0] leds;

00:10 <|{ame>    reg [23:0] counter;

00:10 <|{ame>    always @(posedge clk)

00:10 <|{ame>      begin

00:10 <|{ame>         counter<=counter+1;

00:10 <|{ame>      end

00:10 <|{ame>    assign leds[7:0]=counter[23:16];

00:10 <|{ame> endmodule

00:10 <|{ame> give the following warning?

00:10 <|{ame> ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").

00:11 <|{ame> (yosys compiled from git)

00:21 <so-offish> I finally got a workstation in for all things FOSS FPGA

00:21 <so-offish> So happy.

00:47 <jevinskie[m]> <lofty> "It also helps if your toolchain..." <- Reminds me, I promised someone else this week I’d do an automatic decompilation of the Quartus binaries and spit out all the option names passed to calls to cfg_*

04:55 <|{ame> on ice40-hx8k, how do you enable pull ups?

04:56 <cr1901> I think you have to instantiate an SB_IO directly, and enable the pullup parameter

05:06 <|{ame> is it a block for each input pin?

05:06 <|{ame> I verified this works http://joshhead.net/posts/icestorm-notes.html

05:06 <tpb> Title: Josh Headapohl (at joshhead.net)

05:15 <cr1901> Yes, needs to be done for each pin that you want to enable the pullup

05:19 <|{ame> thank you!

06:15 <tnt> you can also set -pullup yes in the PCF.

07:32 <lofty> |{ame: the ABC warning is harmless; ignore it

07:33 <lofty> (the real answer is that Yosys hasn't passed any flops to ABC, but calls a sequential optimisation pass)

08:02 <|{ame> tnt: thanks,that worked

08:03 <|{ame> lofty: thank you

08:03 <lofty> |{ame: which Yosys flow are you using, by the way?

08:03 <|{ame> git version

08:04 <|{ame> with a ice board

08:04 <|{ame>  Yosys 0.29+11 (git sha1 d82bae32b, gcc 11.3.0-1ubuntu1~22.04 -fPIC -Os)

08:04 <lofty> You should consider using `synth_ice40 -abc9`

08:05 <lofty> Maybe with `-dff` as well

08:05 <|{ame> I am now using yosys -p "read_verilog -noautowire $(SOURCES) " -p "synth_ice40 -blif $@"

08:12 <lofty> |{ame: there's a more idiomatic way of doing that, but sure

08:13 <lofty> You should add `-abc9 -dff` to the `synth_ice40` call

08:13 <|{ame> what's the proper way? I just cobbled up a makefile, but I'd love to do things the proper way if there's one

08:14 <tnt> more importantly the -blif output makes me think you still use arachne-pnr ?

08:14 <|{ame> yes,I do

08:15 <|{ame>  arachne-pnr -d 8k -p $(CONSTRAINT) -P ct256 $< -o $@

08:15 <lofty> Yeah, no, you should use nextpnr

08:15 <lofty> arachne-pnr has been dead for years

08:16 <lofty> |{ame: if you just pass source files on the command line, Yosys will default to calling `read` on those files

08:16 <lofty> So you can do `yosys -p "synth_ice40 -abc9 -dff -blif $@" $(SOURCES)`

08:17 <lofty> But yes, you should use nextpnr; it's so much faster, and it's also maintained

08:22 <|{ame> thanks guys,I switched to it, and, indeed, for one case in which arachne could not route, nextpnr worked without problems

08:23 <lofty> It's also a lot faster, isn't it? :P

08:23 <|{ame> it is, no more route passes filling the compilation buffer!

08:24 <lofty> I mean, nextpnr is still kind of noisy, but it's fine :p

11:30 <Guest66> hello how to remove assign sentence?

11:42 <Guest66> How to eliminate "assign" after synthesis?

12:27 <Guest66> How to eliminate "assign" after synthesis?

12:28 <xiretza[m]> asking once is enough, if someone has an answer they'll tell you

12:32 <Guest66> sorry

13:13 <Guest66> 9.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

13:13 <Guest66> ERROR: FF AsyncQueueSink.$auto$ff.cc:266:slice$652898 (type $_DFF_PP0_) cannot be legalized: dffs with async set or reset are not supported

13:13 <Guest66> how to solve it?

13:22 <tnt> Don't use async FF ... it's not supported in whatever technology you're trying to use obviously.

16:15 <so-offish> jevinskie[m]: What are you using for decompilation and how do I find out more about that