ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<lofty> so-offish: a bitstream for what? Xilinx 7 Series?
<lofty> FASM is distinctly a SymbiFlow-ism, and doesn't really exist outside of it
<jevinskie[m]> <so-offish> "So it looks like I'm interested..." <- There have been a few efforts to go from bitstreams to other representations but they’re device/family specific. https://github.com/VoidMercy/Lattice-ECP5-Bitstream-Decompiler
<jevinskie[m]> I suspect you might want to then try out something like https://github.com/emsec/hal to make more sense of it. hal doesn’t support FASM though, looks like it can import hgl (dunno what that is), liberty (registration gated “open” standard), verilog and vhdl
<jevinskie[m]> I guess this is what HGL looks like but who knows what tool generated it https://github.com/emsec/hal/blob/master/tests/test_utils/gate_libraries/test.hgl
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<so-offish> lofty: I have one on ECP5 and one on XC7 FPGA
<so-offish> jevinskie[m]: Thank you; I will look at that. It looks like it operates on netlists. I will take a look, thank you.
<jevinskie[m]> * “open” standard from Synopsys), verilog
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<lofty> so-offish: FASM is not a thing on ECP5
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<Guest19> hello all, I am having an issue where I can load yosys thru oss-cad-suite..?
<Guest19> I am working on Linux and typed source ... /oss-cad-suite/environment
<Guest19> then typed yosys but permission denied..
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