ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<so-offish> Can you dynamically reconfigure the PLLs in ECP5 like you can with an MMCM?
<so-offish> I've looked at the FPGA library, and the technical support lines I just... I guess I just don't believe it.
<so-offish> I'm too Xilinx centric and my brain can't process a clocking element without a dynamic reconfiguration port.
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