ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<|{ame> is there any way to lower the level of the output from Info to Warning? (i.e. print only warnings)?
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<gatecat> |{ame: in case you're checking the logs, it's "-q" on the yosys command line
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<so-offish> I spoke too soon - when I build with Clang I got the GUI not functioning at all. With GCC I can do pack/place/route, but it hangs when I try to write the bitstream (from the GUI). Headless works tho (fortunately), so it's not a blocker
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<so-offish> Got around it. Switched back to openbox/lxqt to try it and now the save window pops up fine. Weeeeird.
<lofty> To be fair, gatecat and I both use it in headless mode :p
<gatecat> if you just want to inspect a place and route design you made in headless mode, you can add "--write postpnr.json" to your headless config to save a postpnr json; and then run "nextpnr-ecp5 <device arguments> --json postpnr.json --gui" to open a GUI displaying it
<gatecat> it gets you the visualization without needing to click through pack/place/route every time
<so-offish> gatecat: That's a good idea, I'll add that to my scripts, ty
<so-offish> lofty: I'm clearly not on that level :)
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<so-offish> So it looks like I'm interested in going from bitstream <-> verilog. Could I use readbit to get a FASM file, then from FASM to structural verilog?
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