ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<|{ame> hello, sorry for the dumb question. I did read the manual, but besides -flatten, I didn't find anything related to multiple submodules. How should I compile a project with submodules?
<gatecat> |{ame: any more details on what you need to do? most of the synthesis flows should deal with them already, usually by flattening
<|{ame> gatecat: I think I found it.
<|{ame> I had a file main.v
<|{ame> which inside instantiates sub sub(....)
<|{ame> and sub is declared in sub.v
<|{ame> My Makefile was
<|{ame> %.json: main.v
<|{ame>  ghdl -a UART_TX.vhd
<|{ame>  ghdl -a UART_RX.vhd
<|{ame>  yosys -p "plugin -i ghdl; ghdl UART_TX; ghdl UART_RX; synth_intel_alm -top spiga -nodsp -nobram; write_json $@" $^
<|{ame> and simply changing it to
<|{ame> %.json: *.v
<|{ame> it worked
<|{ame> I do not know if this is the proper way to do it though
<xiretza[m]> it's not, the make target should depend on the files that are actually required, so main.v sub.v in this case
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<Guest66> hello! The following error appeared while using yosys. How to solve it?
<Guest66> ERROR: Value conversion failed: `1 'd0'
<Guest66> thank you
<Guest66> when read_verilog
<jix> Guest66: can you share more of the input that triggers this error?
<Guest66> here
<tpb> Title: Sign in to your account (at postechackr-my.sharepoint.com)
<Guest66> and when I ran other verilog file, error has occurred. what is mean?? ERROR: syntax error, unexpected TOK_ID
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<jix> Guest66: which yosys version are you using?
<Guest66> Yosys 0.9 (git sha1 UNKNOWN, clang 10.0.0-4ubuntu1 -fPIC -Os)
<jix> that is an ancient version, the link you shared loads without errors in a recent version
<Guest66> thx how to upgrade?
<Guest66> and I have a separate question. Does yosys not consider SDC files?
<jix> https://github.com/YosysHQ/oss-cad-suite-build#installation is the easiest way to stay up to date
<Guest66> really thank you
<Guest66> have a nice day
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<lofty> Aww, I missed a synth_intel_alm user in the wild
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<so-offish> lofty: What's synth_intel_alm?
<so-offish> lofty: Cyclone V synth (sorry just Googled it)
<lofty> lofty: written by yours truly
<lofty> so-offish: ^
<so-offish> lofty: Very cool! If you ever want to talk about it I'd be interested.
<lofty> so-offish: what would you like to know?
<so-offish> lofty: Can I ask where you started? I mean, was this a techlib for Yosys as a first step, or was there some other first step in the process? I'm trying to think about like "how I would start" if given the same project, and I'm not sure I'd know where to begin
<lofty> so-offish: the first step is mostly to look at the vendor primitives and what can be implemented in hardware
<lofty> Then one can implement LUTs and DFFs
<so-offish> lofty: That would be from a project similar to prjxray, but for Intel parts, correct?
<lofty> Actually not really
<lofty> (you're referring to project Mistral, by the way :p)
<so-offish> lofty: (Thank you; I'm getting up to speed on all the various projects, appreciate the correction)
<lofty> Anyway
<lofty> The vendor primitive library gives a few hints, but one can also "just try it and see"
<lofty> One particularly fun thing to learn is that the flops on a Cyclone V initialise to zero only
<lofty> Which means you can't have a flop that initialises to zero with an async set
<so-offish> lofty: Just ran into something similar on the ECP5! I thought I was in crazy town.
<lofty> so-offish: hmm, on ECP5 it's a boy different
<lofty> *bit
<lofty> On ECP5 the initialisation value and the reset value must agree; that is, a flop that initialises to zero must have an async clear
<so-offish> Let me see, what was I trying to do - I was trying to initialize a FF to a certain value post configuration and found that wasn't supported (or at least I thought) - in this case, it's specific to being unable to async set?
<so-offish> Ahhh
<lofty> This is subtly different to the Cyclone V, because the ECP5 can model initialisation to 1 just fine
<lofty> But for Cyclone V you emulate this using inverters that Yosys silently adds for you
<lofty> They have the same overall functionality though
<lofty> Anyway
<so-offish> The ECP5 can do that? Hm, I thought I had a relatively simple test case where I couldn't detect any difference in the Yosys outputs...
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<so-offish> Maybe I should go re-run my test case before I speak out of turn
<so-offish> haha
<lofty> Sure it can do that
<so-offish> lofty: Ah; interesting that Yosys achieves the same thing with injected inverters. Pretty smart.
<lofty> Now, I set out to do something that is equal parts brave and dumb
<lofty> I use ABC9 in synth_intel_alm
<lofty> Despite it being...quite flaky
<so-offish> Well...it was an academic showpiece, right?
<lofty> And to be fair, it's a pretty effective showpiece
<lofty> But one does run into a lot of ABC9 bugs
<so-offish> Oh extremely; it wasn't intended as a knock
<lofty> Now, the relevant information, well, fell off the back of a truck
<so-offish> The best place to get hard to discover information is from the back of trucks. This is known.
<lofty> It also helps if your toolchain has a secret debug option to deserialise your databases into plain text and you left that on release
<lofty> But Altera wouldn't be stupid enough to do that
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<Sarayan> you can't really insert an inverter when the ff is on the output of the adder though
<so-offish> LOLOL
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