ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<lofty> so-offish: can you paste your Verilog somewhere?
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<so-offish> lofty: Yeah lemme get that cleared but should be fine brb
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<so-offish> I think I figured out why what I was doing caused an error
<so-offish> When using TRELLIS_COMB with IS_Z1=1'b1, I had FCI's input tied to 1'b0 - instead I just commented out that input, and I was able to get to routing
<so-offish> Routing still failed, but that's a new problem
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<so-offish> No wire found for port F1 on destination cell COMB2.
<so-offish> Bang head on keyboard.
<so-offish> ERROR: Wire X60/Y49/F5_SLICE is used as source and sink in different nets: w0 vs w3
<so-offish> Ok, so there must be something I don't know about the way these wires are used between cells (?)
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<so-offish> Wait, for the ECP5, is one comb the IS_Z1=1'b0 and the other is IS_Z1=1'b1, for a given slice?
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