<lofty>
so-offish: can you paste your Verilog somewhere?
FabM has joined #yosys
FabM has joined #yosys
FabM has quit [Changing host]
SpaceCoaster has quit [Quit: Bye]
SpaceCoaster has joined #yosys
kraiskil has joined #yosys
kraiskil has quit [Ping timeout: 240 seconds]
krispaul has joined #yosys
kristianpaul has quit [Ping timeout: 265 seconds]
leohoo_sdu[m] has joined #yosys
leohoo_sdu[m] has left #yosys [#yosys]
SpaceCoaster has quit [Ping timeout: 256 seconds]
SpaceCoaster has joined #yosys
SpaceCoaster has quit [Ping timeout: 265 seconds]
SpaceCoaster has joined #yosys
<so-offish>
lofty: Yeah lemme get that cleared but should be fine brb
so-offish has quit [Ping timeout: 256 seconds]
DaKnig has joined #yosys
somlo has quit [Ping timeout: 240 seconds]
somlo has joined #yosys
so-offish has joined #yosys
<so-offish>
I think I figured out why what I was doing caused an error
<so-offish>
When using TRELLIS_COMB with IS_Z1=1'b1, I had FCI's input tied to 1'b0 - instead I just commented out that input, and I was able to get to routing
<so-offish>
Routing still failed, but that's a new problem
so-offish has quit [Ping timeout: 240 seconds]
so-offish has joined #yosys
so-offish has quit [Read error: Connection reset by peer]
so-offish has joined #yosys
somlo has quit [Ping timeout: 268 seconds]
somlo has joined #yosys
<so-offish>
No wire found for port F1 on destination cell COMB2.
<so-offish>
Bang head on keyboard.
<so-offish>
ERROR: Wire X60/Y49/F5_SLICE is used as source and sink in different nets: w0 vs w3
<so-offish>
Ok, so there must be something I don't know about the way these wires are used between cells (?)
so-offish has quit [Read error: Connection reset by peer]