ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<singham> Folks, OpenFPGA uses skywater-pdk.
<singham> How are the final designs made? The placing of gates, their libraries and connection of wires?
<singham> I wanted to know more about physical design if some of you know more
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<singham> Why is the cost of making photomasks so high?
<singham> I saw cheapest foundaries have been setup for $5M only
<singham> And I see on Wiki that photomasks can go around $40M - $100M
<singham> I mean come on!
<so-offish> Depends on the number of them you need, the resolution you're trying to hit, etc
<so-offish> also there's some sophisticated processing algorithms that go into them nowadays
<so-offish> Because of multipatterning and edge effects
<singham> But still $40M ? Give me a million and I'll write it for you from scratch in the language you want.
<singham> I mean it's like a 4 cm^2 thing.
<so-offish> So I hand you the algorithm and you... translate it for $1M? lol
<singham> :D
<singham> I'll create the algo. No worries
<singham> At $1M it is doable
<so-offish> Oh your background is computational optics?
<singham> Naah. I took a course in computational physics though
<singham> nvm
<singham> Aah wait
<singham> It's written, "new mask shop"
<singham> Mask cost from $250 to $100k
<singham> in 2006
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<singham> Typically, FPGAs have how many layers in it's IC?
<singham> Say, a chip like iCE40?
<singham> Like, there is a transistor, on top of it will there be more?
<knielsen> singham: There's only one layer of transistors on a chip. On top of that are multiple layers of routing ("wires"), Don't know any numbers, but I think 10-20 layers of routing is not uncommon
<singham> Wow. 10-20 layers!
<singham> All chips have just 1 layers of transistors?
<singham> knielsen: Thank you.
* singham will see you fine hobbits later
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<Sarayan> 10-20 is a lot actually
<Sarayan> iirc the latest wafers we've done are something like 7 metal layers?
<Sarayan> (european project, finnish partner)
<Sarayan> also, a cmos wafer run for a reasonable node is something like 100K nowadays, not millions
<Sarayan> here you can see real prices for mpw runs where you pay by square millimeter: https://europractice-ic.com/schedules-prices-2023/
<tpb> Title: EUROPRACTICE | Schedules 2023 (at europractice-ic.com)
<so-offish> 100k is an ancient node though, isn't it?
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<Sarayan> I think it's 28nm or something around that
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<Sarayan> which is good enough for a lot of stuff already, in fact
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<whitequark> even 65 can be okay still, though i think it gets hard to justify for battery powered stuff