<azonenberg>
it might be fun to pick up one of these and make a little test board
<azonenberg>
14 bit 50 Msps for $30
<azonenberg>
this is the lowest cost JESD204 ADC I've found yet
<azonenberg>
Might be nice to go get some experience with the protocol before doing work with the big boys like the AD9213
<azonenberg>
Buuuut I don't need more projects
<azonenberg>
i need to finish the stuff i've already started :p
<Degi>
I kinda wonder if you can make a SERDES by combining a few ordinary IO, at least for like 2-3 Gbps
<azonenberg>
combining how?
<azonenberg>
I was able to do differential MLT-3 at 125 Mbps, with pre-emphasis, on a spartan-6 using ordinary GPIOs
<Degi>
Like if you can sample an IO at maybe 3 GS/s you could combine 3 IOs with on-chip delays to get 9 GS/s and then use some algorithm to do CDC
<Degi>
Ooh, a multi-level signal
<azonenberg>
The highest I'm aware of having been done successfully was a Xilinx appnote using one LVDS input using an IBUFDS_DIFF_OUT feeding into two ISERDES's with 90 degree phase offset
<azonenberg>
which gives you 4x oversampling of the input
<azonenberg>
the net result is 5 Gsps, enough to do oversampling CDR of a 1.25 Gbps input
<Degi>
Oh neat, it can feed one IO to multiple SERDES
<azonenberg>
exactly two
<Degi>
Why do you need a 4x oversampling to do CDR?
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<azonenberg>
because there's two IOBs in a diff pair
<azonenberg>
so you can use the ISERDES of each half
<Degi>
Ah nice
<Degi>
Hmm, maybe I can play around with that sometime soon. Especially since the ECP5 only has up to 4 SERDES, somehow making more in fabric would be fun, even if it only works to like 1 Gbps
<azonenberg>
anyway there's an appnote sampling SGMII with that
<Degi>
Oh neat
<azonenberg>
This depends on having the ISERDESE2 or equivalent I/O serialization stuff
<Degi>
Hmm, the ECP5 has a lot of split by 2 or 4 SERDES which need a clock signal and do no CDR by themself and an adjustable time delay (on each IO?) in 127 * 25 ps steps
<azonenberg>
that's the point with the ISERDES approach
<azonenberg>
if you oversample by 4x, 2 of the 4 samples are close to transitions
<azonenberg>
and the other 2 are near the middle of the data eye
<Degi>
Ah I see
<Degi>
I wonder if that might work with an OSR of 3 or maybe only 2 if some bit errors are acceptable and if there are a lot of transitions
<Degi>
Or even with an OSR of 1 if you can keep the clock on both ends phase coherent and then during initialization vary the delay until it errors a lot, which it should do when it hits an edge, and then set the delay to the middle of two adjacent values where it errors a lot. Though I guess this requires a known pattern for initialization. And then hope that voltage and temperature changes don't change the delay too much
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<someone-else>
Degi: 2-3gbps over ordinary IOs will probably be problematic because of IO capacitance, which is kinda bad on most FPGAs
<someone-else>
i.e. deterministic jitter would not be nice
<Degi>
Hm yeah probably, combined with 0.3 UI jitter on the ADC side