<azonenberg>
MEAD assembly update: 14 fully assembled, two more flashed and just need LCDs installed
<azonenberg>
Two failed after rework (still the 3.3V rail, but stubborn enough that a casual dab of solder didn't fix it) and are on deck to be redone over the weekend
<azonenberg>
and six more not yet reworked
<azonenberg>
Hoping to finish them all tomorrow
<azonenberg>
and spent a bit more time on it. 19 fully assembled and appear to be OK, three pending rework, two failed initial rework and need further attention
<azonenberg>
As soon as I get those taken care of I can turn my attention to the SMA test board (I think the sims for the key connectors are done, but I need to analyze the results and tweak the layout before ordering a new rev)
<azonenberg>
and assembling the AKL-AD3 tip prototype that's been on my desk for a week
<azonenberg>
And then think about ordering a prototype of the amplifier board
<azonenberg>
Once those are out of the way I'll be done with hardware stuff for a while and can shift gears back to glscopeclient software side
<azonenberg>
At least until the baby arrives...
<azonenberg>
I might also start spending some time thinking about the software stack for MAXWELl
<azonenberg>
MAXWELL*
<azonenberg>
and how the firmware is gonna be architected, perhaps do some initial prototyping of that
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<GenTooMan>
how much FW space do you have?
<azonenberg>
GenTooMan: for which part of the system:
<azonenberg>
There's a total of four programmable chips in play
<azonenberg>
the MEAD pods have a stm32f031 that is using about 11 kB of the 32 kB of flash. It controls the LCD and input threshold DAC and not much else
<azonenberg>
MAXWELL contains an XC7K160T as the main datapath FPGA
<azonenberg>
an XC7S6 as an IO expander and hotswap controller managing power to all of the pods etc
<azonenberg>
and a STM32F777 monitoring all of the i2c sensors, controlling the front panel LCD, and sequencing all of the power rails other than 3V3_SB
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<GenTooMan>
sounds like you have lots of parts with FW :D
<azonenberg>
Yep
<azonenberg>
The XC7S6 gateware is already written and tested in simulation
<azonenberg>
It's basically just a SPI to GPIO and UART expander
<azonenberg>
12 uarts with a register interface to read/write their attached fifo
<azonenberg>
and a bunch of gpios for hotswap
<azonenberg>
the MEAD pod firmware is ~done as well
<azonenberg>
The stm32f777 and kintex7 gateware do not yet exist for the most part
<GenTooMan>
I have a F756 board so my guess is you have the same package options, sounds like you just want a display maybe ethernet and some IO.
<azonenberg>
GenTooMan: It's TFBGA216. it actually runs a zillion i2c buses to different parts of the board
<azonenberg>
i think five total?
<azonenberg>
and spi to the fpga, and a bunch of GPIOs for power rail sequencing
<azonenberg>
i'm using the vast majority of the pins
<azonenberg>
It's taking a lot of the low speed stuff away from the FPGA because after the 64-bit DDR3 SODIMM and 96 LVDS inputs there's not much left