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<Armand>
Anyone care to hazard a guess at what the Asus Tinker V might retail for?
<Armand>
I'm guessing around £60-80.
<jrtc27>
if you want to run a unix on it, don't waste your money
<Armand>
Nah, I'll run Linux.. *trollolol*
<jrtc27>
it violates the specification for virtual address translation
<jrtc27>
in a way that cannot fully be papered over in the kernel
<Armand>
I don't know what that means for running a plain ol' kernel.
<jrtc27>
some binaries just will never be able to be run on it
<jrtc27>
depending on what address they're linked at
<Armand>
Well, the short end is that I'd like to use it as a router.
<jrtc27>
by default they don't work
<jrtc27>
*shrugs*
<jrtc27>
just don't be surprised if $distro_of_choice never quite works properly on it and sees some binaries crash on load
<Armand>
Ohh, I'd expect something custom for the board.
<Armand>
Not some run-of-the-mill.
<Armand>
Besides.. I don't see a display output on the spec. :P
<jrtc27>
if you're building from source you can make it work, provided the kernel support doesn't get rejected
<jrtc27>
(or I guess you could still apply the rejected patches...)
<Armand>
Sorry... Rejected by whom?
<jrtc27>
there is a risk that the patches needed to support that broken-by-deliberate-design SoC get rejected by the riscv and/or mm subsystem maintainers
<jrtc27>
given I suspect that it will have to reach into core mm code
<Armand>
I wouldn't expect that to be a thing.
<jrtc27>
and one linux kernel developer who's done a bunch of mm work recently asked quite sincerely whether it would be easier and cheaper to shred all the fabbed chips rather than have to maintain support for this egregious spec violation
<Armand>
I don't really understand where you're coming from with this, but.. ehh.
<pierce>
I'd love to know what RVI's take on this is
<jrtc27>
"oopsie"
<jrtc27>
they have no teeth
<jrtc27>
they will bend over backwards for any vendor
<pierce>
Slap them on the wrist, sure. But at least tell them to revoke the RISC-V branding
<jrtc27>
I wish
<jrtc27>
or at least say it's RISC-V without Sv39 support but with a non-standard conflicting virtual memory extension that sure looks a lot like Sv39 with a bug
<jrtc27>
because that's technically true
<Armand>
According to what I'm reading, the Linux support might already be there.
<jrtc27>
it's not
<jrtc27>
nobody's even sent a patch to linux-riscv to try and work around this
<jrtc27>
running binaries on that hardware won't check that they aren't linked at an address it doesn't support
<jrtc27>
mmap will happily allocate that virtual address range
<jrtc27>
(whether decided by mmap or the programmer with the hint)
<geist>
jrtc27: oh interesting, the cores in the tinker (Andes Tech something) have some sort of nonstandard paging unit?
* geist
checks their data sheet, now curious
<jrtc27>
yes, it has a magic instruction/data local memory that matches *before* translation
<geist>
wat.
<jrtc27>
the flowchart doesn't include that key info
<jrtc27>
the flowchart is how it would work in a sane world
<geist>
aaah i see. well one could make sure you dont map the address space down there
<jrtc27>
no, that's just boring DMA coherence
<geist>
but that is probably hard coded in freebsd/linux/etc
<jrtc27>
the toolchain picks it for position-dependent binaries (and hard-codes 2 MiB as the start address)
<geist>
but yeah that's basically the no-go on the list. not making an exception,e tc
<jrtc27>
the OS picks it for everything else
<jrtc27>
yeah
<jrtc27>
it's insanely wrong
<jrtc27>
like, nobody with any clue about virtual memory would ever ok that
<geist>
personally i think 0x10000 is a bit low for a default starting address, but that decision was made already, so it's water under bridge
<jrtc27>
I assume it was chosen because it's the lowest
<geist>
yep.
<jrtc27>
so no fragmentation concerns
<jrtc27>
and less arbitrary
<geist>
generally i'd pick the first of a large page block, like 2MB, so that you have some possibility of using a large page to map the segment
<geist>
but then one can still do that in this case, since the OS isn't forcing you to base your binary there
<Armand>
So.. as I don't do Dev.. I'd assume anyone writing code for this would already work around it ?
<geist>
as jrtc27 points out in the email thread, someone could still try to map something there and corrupt bits or whatnot. you'd really need to tell the OS to start the user address space above it
<geist>
which i suspect is fairly hard coded in most kernels
<jrtc27>
it's at least subject to PMP checks so they've made OpenSBI configure the PMP to fault on access to it
<jrtc27>
so it goes from being side channel / hard to diagnose corruption to immediate deterministic fault
<jrtc27>
still doesn't make it work though of course
<geist>
yah. at least the PMP behaves!
<jrtc27>
yeah... I would not have been at all surprised if it bypassed that too
<jrtc27>
if anything it makes their implementation *more* weird
<Armand>
Well, it seems a bit of a meh to me.. at least from the perspective of a non-codey guy.
<Armand>
I'd assume anyone smart enough to dev for it, would already be aware of it.
<geist>
problem here is you can distribute binaries that will simply crash on this machine
<geist>
so some debian distro or whatnot would have broken bianries
<geist>
well, non functional. they're perfectly good binaries
<Armand>
I'm pretty sure there won't be much in the way of a distro going on it. :P
<jrtc27>
they claim it supports debian and fedora(?)
<geist>
well, no reason you couldn't try to run debian or something on it
<jrtc27>
in their marketing
<jrtc27>
so... the fact it doesn't is pretty important
<Armand>
fuck knows.. I guess I'll find out at some point.
<geist>
yah, if it's a reasonably functional core if there's a kernel working, a debian should load
<Armand>
I mean, hell... look at the Ox64. :P
<geist>
yah
<geist>
OTOH looks like the debian on my vf2 is using ASLR so it probably doesn't hit this *except randomly*
<geist>
but maybe there are some non aslr binaries, perhaps in early boot phase
<jrtc27>
static binaries will be PDEs, I don't think riscv glibc (any glibc?) has static PIEs
<jrtc27>
surely there's at least one on your system
<Armand>
That's fine.. I'm already stocked on pies. :D
<geist>
yah i'm guessing maybe some early initrd or whatnot is
<jrtc27>
yeah, tends to be
<jrtc27>
*mumble* klibc perhaps
<jrtc27>
though that's been hacked up to be less narrow-minded these days
<jrtc27>
I think it sort of does dynamic linking now
<jrtc27>
though best you don't know some of the horrors there...
* jrtc27
was involved with making that work for ia64...
<geist>
yah, init is systemd in this machine so it's all over the place, but makes sense
<dh`>
what on earth did they do? boggle
<Armand>
Ohh, that's easy, geist.. Just SysV that sucka!
* Armand
ducks
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<geist>
heh, well, it's the default one from starfive, apt-get updated
<geist>
haven't really tried to sit down and get something else on it
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<geist>
mostly at this point just want a riscv linux machine to run some benchmarks and write test code on, and then port my stuff to it
<Armand>
Have you looked at the Ox64 yet?
<Armand>
Limited, but the support is getting there.
<jrtc27>
I should figure out some freebsd drivers for the vf2 now that I've pinpointed https://github.com/starfive-tech/VisionFive2/issues/33 (three levels of brokenness there... any one of them being missing would have papered over the issue, some more silently than others)
<geist>
hmm, i see it, but honestly not that interested in C906 based designs. already have a nezha , which is an allwinner d1
<geist>
whocih is a C906
<Armand>
Not seen that one yet.
<jrtc27>
the syscon crud on this terrifies me though, sounds like way too many random system registers to go frob just to make the board do anything useful
<jrtc27>
but maybe you don't need all that much for most things to work
<Armand>
Ahh, yes... Quite a bit more expensive. :P
<Armand>
The Ox64 cost me £20 all-in, inc shipping and whatnots.. can't really argue with that, for a toy.
<geist>
oh totally
<jrtc27>
pine64 wiki says RV64IMAFCV... I think not
<Armand>
I not think.
<geist>
i thought the T head stuff has their own wonky Vector stuff
<Armand>
Dunno.
<Armand>
Seems the community are doing all the things, so.. ehh.
<geist>
which obviously isn't the Real V, but i can see why someone thought that meant you can add 'v' to the end
<Armand>
Looks like Linux support with networking and SSH client is mostly there.. I think I'm waiting on HID keeb support.
<geist>
the one sort of saving grace is the t-head verilog is open source. so yo ucan always refer to that :)
<Armand>
Not checked in a while.
<geist>
at least for the 906
<Armand>
that's all above my paygrade :P
<jrtc27>
yes, it's not V
<Armand>
I can throw around all the Linuxy-bits and do the hardware work.
<jrtc27>
and it has D
<Armand>
Codey-things, I don't care about.
<jrtc27>
should be RV64IMAFDCXtheadv or whatever the thing is called
<geist>
yah to be fair i think the thead docs do at least call it what it is
<pierce>
<jrtc27> "should be RV64IMAFDCXtheadv or..." <- I don't know why they rebranded it
<pierce>
There provision in the ISA string spec to specify versions
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<jrtc27>
because drafts are special
<Armand>
... Just attach a draft excluder to your door.
<Armand>
:P
<geist>
been reading the frame pointer layout and Zcmp and whatnot discussion all over again as we're trying to figure out if we want to diverge on that for fuchsia
<geist>
thus far no but the Zcmp thing being backwards from the frame pointer layer is maybe an issue
<geist>
ah looks like someone on our team posted on the github issue just today
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* bjdooks
wonders if he should ask conchuod for some more polarfire tshirts to wear during horsecreek work
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* geertu
finds lots of "Polar Fire" T-shirts on AliExpress
<bjdooks>
geertu: i was too late to raid the set from the riscv summit in december
<bjdooks>
:(
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