sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<unlord> hi
<unlord> What is the current version for rv64i ?
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<conchuod> unlord: current version of what?
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<somlo> palmer: you were right about my litex blobs overwriting each other in RAM. Turns out, even though opensbi's own criteria are met (https://github.com/riscv-software-src/opensbi/blob/master/docs/firmware/fw_jump.md?plain=1#L38-L57), unless I explicitly request the opensbi-produced DTB to go higher than the default, parts of my kernel will get clobbered :)
<somlo> that took care of *part* of my problem
<somlo> note to self: I should check out how qemu's built-in opensbi blob is configured :)
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<unlord> mtinman[m]: thanks!
<mtinman[m]> unlord: NP! Glad to help.
<unlord> how about a harder question, if I wanted to write some RVV optimizations, how do I profile them?
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<mtinman[m]> <unlord> "how about a harder question..." <- Using LLVM, or Clang?
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<mtinman[m]> AFK for now...
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