sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<marvinXP> Hi. The VisionFive2 Core complex manual doesn't define "Latency" and "Repeat rate" for the floating point instruction timing. Do I understand it right that latency is how long to wait (counted in the following instructions repeat rate) before reading something written? And repeat rate being 1 for everything except div and sqrt means that the next instruction will start making progress the next clock cycle?
* bjdooks wonders why people just don't use the CLINT for clock source
<marvinXP> And that because these tables are only for floating point, that I should assume everything else has repeat rate 1, and everything not in the table on page 60 is 1 latency, 1 repeat rate?
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<rneese> Good Mornig
<rneese> Esmil you around this am
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<rneese> ok using the update tool I get ERROR: 0xfffffffe, exceeds the available size in flash, updata fail when it tries to flash the u-boot-spl
<rneese> nm fixed it
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<rneese> new fwfor the vf2 is out
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<pierce> ah this is pretty groovy https://github.com/google/cpu_features
<pierce> RISC-V is only on Linux apparently
<pierce> and there doesn't seem to be mechanisms to detect Zba and family
<rneese> no freebsd runs on the unmatched
<rneese> but it seems otherboards like the work for beaglev starlight where ended when the stalight was discontinued
<Tenkawa> rneese: he's talking about that tool..
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<Tenkawa> its on the webpage listed above
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<rneese> ok
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<conchuod> @pierce Doesn't look like it'd be too difficult to add zba/zbb though?
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<conchuod> Actually, as that reads /proc/cpuinfo, it's not gonna find zba since Linux doesn't yet do anything with zba...
<conchuod> So apologies!
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<pierce> <conchuod> "Actually, as that reads /proc/..." <- meanwhile Zbb was merged in a few days ago https://github.com/torvalds/linux/commit/01687e7c935ef70eca69ea2d468020bc93e898dc
<conchuod> Yah, hence me saying zba ;)
<conchuod> Adding zbb support to their stuff, should be easy though!
<pierce> i find it a bit odd that they didn't add in the others while they were there 😕
<pierce> unfortunately it's just delaying adoption of the extensions in userspace...
<conchuod> I scanned the PRs/issues, and it looked like they weren't super interested in things that userspace would not be able to use.
<conchuod> So I guess that's why some extensions were left out
<conchuod> and since zbb etc were not upstream, they got dropped too
<conchuod> Although, they added zicsr & zifencei that don't appear in /proc/cpuinfo!
<pierce> well there's a JIT atm that isn't detecting Zba/Zbb properly due to this conservatism
<conchuod> It's just a oneliner patch to add it, no?
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<pierce> <conchuod> "It's just a oneliner patch to..." <- according to the patch i linked, there's a bit more plumbing required, not to mention updating the device tree for the boards that actually have it
<pierce> <pierce> "ah this is pretty groovy https:/..." <- oh for this it should be 1 (or effectively 1), you're right
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<conchuod> There's no devicetrees that need it but don't have it afaik
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<conchuod> pierce: ahh you meant zba in Linux, yeah that's more than a one liner - but to inform userspace it's not all that much more
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<ch> conchuod: feels like the second one might have wanted to be mutex_unlock?
<conchuod> ch: that's very silly
<conchuod> I'll go fix that now, do you have an email for a reported-by?
<ch> Chris Hofstaedtler <zeha@debian.org>
<conchuod> ch: thanks for spotting my silliness
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<geist> interesting, anyone off the top of their head know how many ASID bits the visionfive 2 implements in the cpu?
<geist> i've noticed that linux seems to disable ASID use because it has probed and decided that it's too low, but doesn't print it out
<geist> the threshold is pretty low, needs to support more ASIDs that 2*NR_CPUS, which means only 4 bits
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<ch> conchuod: sure, glad to help!
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