sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<mmind00> conchuod: https://github.com/mmind/riscv-vector-test ist the (very simple and ugly) sample I used ;-)
<mmind00> Finding a really simple program to "just run some vector instruction" somehow proofed difficult initially
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<urs> mmind00: you need a pretty bleeding edge clang and a somewhat convoluted set of command line instructions, if you want to get it to emit any vector instructions from c/c++ code
<urs> "-march=rv64imafdcv -mllvm --riscv-v-vector-bits-min=256" was the minimum I could come up with for it to create anything.
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<conchuod> mmind00: usually end up writing some inline asm for testing stuff, so nice not to have to this time :) thanks
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<mmind00> urs: the sample I used, did just implement the vector parts in asm ... running complex vector programs on the c9xx cores (d1 and friends) will require more acrobatics for usersapce - due to c9xx implementing vector-0.7.1 and _not_ the real vector-1.0
<mmind00> urs: i.e. my goal was to allow the kernel to handle both, so "any" vector sample was fine for me :-)
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