sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
<rneese> something like this
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<drewfustini> Asus choose Renesas (and this that Andes core) for their RISC-V single board computer https://liliputing.com/asus-tinker-v-is-the-companys-first-single-board-pc-with-a-risc-v-chip/
<bjdooks> is that the one with the wildly idiotic tcm?
<drewfustini> Yeah
<drewfustini> So those patches will get a good workout
<drewfustini> Andes AX45MP
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<mtinman[m]> <bjdooks> "is that the one with the..." <- TCM?
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<palmer> tightly-coupled memory
<palmer> in this case it's got the TCM that circumvents address translation, which makes a mess for Linux
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<mtinman[m]> palmer: TY for clarifying that...
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