sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<berte> hello everyone I'm trying to compile sifive-unleashed u-boot sources however I'm getting the required opcode errors event though my gcc includes those opcodes --> https://dpaste.com/9SFV822ZS , any idea would be great, thanks :)
<ch> "extension `zicsr' required" means that extension needs to be enabled for your target
<berte> Hi ch thanks for your reply but I'm cross-compiling on an x86_64 intel machine but the target hardware will already be riscv64
<berte> even more interesting is that I compiled a simple c file with the same compiler and it is now running smoothly on the device
<drmpeg> berte: Here's the patch. https://www.w6rz.net/arch.patch
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<berte> drmpeg, thanks for your reply I just found the same patch a few minutes ago :)
<drmpeg> I don't think it ever got merged into u-boot.
<berte> yes it's missing
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