sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<Xav101> Hey, is there some way to tell from FUNC7 whether or not an instruction uses bits 11-7 as rd or not?
<Xav101> Not seeing any obvious pattern in the func7 field for that
<Xav101> (Obviously you could check func7 against all possibilities for valid instructions to see whether or not it has a destination register or an immediate there, but I'd hope there's a simpler solution_
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<zx2c4> palmer: wondering - do you want to pick https://git.zx2c4.com/wireguard-linux/commit/?id=99a1a96f1f80b68b0fb5156ff6bd3f0973cd1f4d into your riscv fixes tree or should i send this via netdev?
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<palmer> zx2c4: I'm fine either way
<zx2c4> palmer: alright, well could you take it then (preferably without maiming the commit subject)? net.git path takes longer
<palmer> OK, I don't have the mail. Do you have a lore link or somethinG?
<zx2c4> no, i just pasted that cgit link into my reply to your pull request. i'll post it for realzes now
<palmer> thanks
<zx2c4> sent.
<zx2c4> lore link will be https://lore.kernel.org/linux-riscv/20220809145757.83673-1-Jason@zx2c4.com/ whenever lore catches up
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<zx2c4> palmer: ahh there it goes, ctrl+shift+R on https://lore.kernel.org/linux-riscv/20220809145757.83673-1-Jason@zx2c4.com/ and now its on lore
<palmer> thanks. I'm assuming there's no way to make this include the rv32.config we've got in arch? that way this won't happen again
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<zx2c4> palmer: no, not possible; wg CI configs are minimal and custom
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<palmer> OK, so that ".config" isn't an include like arch/riscv/configs/32-bit.config , it's just a standalone defconfig?
<zx2c4> not quite. it's a fragment that's combined with some other fragments and things generated by a makefile
<palmer> OK, so I guess what I'm getting at is: should I add this to my CI?
<zx2c4> oh, sure, if you want. that part is easy:
<zx2c4> ARCH=riscv32 make -C tools/testing/selftests/wireguard/qemu -j$(nproc)
<zx2c4> ARCH=riscv64 make -C tools/testing/selftests/wireguard/qemu -j$(nproc)
<zx2c4> that'll build userland, kernel, load it up in qemu, execute it, look for success
<palmer> OK, I'll add it to the TODO list
<zx2c4> this is what's running on https://www.wireguard.com/build-status/
<palmer> oh, even better ;)
<palmer> is that pointed at my for-next?
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<palmer> I see a linux-next one
<palmer> if there's some way to sign up for email when the RISC-V bits fail that'd be awesome
<vagrantc> are there in-progress patches submitted to linux for starfive/jh7100-starfive-visionfive-v1.dtb allwinner/sun20i-d1-lichee-rv.dtb or allwinner/sun20i-d1-nezha.dtb ?
<palmer> vagrantc: nothing showed up from searching my inbox
<zx2c4> palmer: it gets your for next via linux-next, yea
<zx2c4> not a bad idea about email notification. i'll look into that
<palmer> zx2c4: cool, thanks. that way I don't have to poll for failures
<palmer> I might add it anyway, because I like to get stuff before I merge it, but having the bot is super nice as it'll test other bits too
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<conchuod> vagrantc: that's in the soon TM category, smaeul_ I believe is waiting for other bindings etc to be merged first
<vagrantc> conchuod: thanks
<Esmil> palmer: there is a patch for the unmatched devicetree. it'd be cool if that could make it into 5.20 now that the LED patches made it: https://lore.kernel.org/linux-riscv/20220705210143.315151-5-emil.renner.berthing@canonical.com/
<conchuod> Is this gang-up-on-Palmer-with-patches o clock? I can joig in with that haha
<palmer> conchuod: unfornutaly the compiler folks have booked yelling at me this morning, so you'll have to wait until after they're done ;)
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<conchuod> I was joking palmer but I can drop some links in here later on... There's a few reviewed fixes I've seen here and there.
<palmer> thanks
<palmer> I was hoping to merge stuff today, so that'd be helpeful
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<palmer> and looks like the compiler folks weren't even all that mad at me, so maybe I can get some real work done today ;)
<conchuod> palmer: don't ask me where it was, but there was some talk about reviving the riscv patchwork.. would that be helpful?
<palmer> in theory yes, but in practice it seems like patchwork never stays accurate enough so it's just another source of confusion
<palmer> last time I couldn't get the command-line cllient working smoothly enough, not sure if it's better these days
<conchuod> hmm. well if you ever do decide to try it out again I'd be happy to help fill in the gaps on what it doesn't pick up on automagicly if it made things easier palmer (:
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<conchuod> `pattern: rv64imaf?d?c?h?(_z[imafdqcbvkh]([a-y])*)*$` !someone save me!
<conchuod> I assume for completeness there should be more optional letters after h?
<conchuod> s/after/before
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<LetoThe2nd> question for understanding, please. is the sbi mandatory in the (linuxoid) riscv boot process? or who decides if it shall be loaded?
<LetoThe2nd> repectively - if I have a soc that provided M-mode (?), then the soc provider defines the sbi to be used?
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<jrtc27> SBI is the interface between M-mode and S-mode
<jrtc27> if you want to run a Unix-like OS in S-mode then you need an implementation of that interface
<jrtc27> if you're running M-mode Linux then there's nothing beneath it to talk to so there is no such implementation present, Linux just pokes everything directly
<LetoThe2nd> jrtc27: ah okay. so is the mode linux runs in something i can freely choose (today)? or is the choice more like a theoretical construct, and all real life implmentations have agreed on S-mode?
<jrtc27> M-mode Linux is for microcontrollers without an MMU
<jrtc27> it's a very limited environment and a compile-time option
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<LetoThe2nd> jrtc27: ah okay, thanks!
<dh`> iirc the only thing from SBI that you _really_ need is the timer goop
<jrtc27> for non-v0.1 you need it for SMP
<jrtc27> timer stuff is superseded by the Sstc extension
<jrtc27> but starting secondary harts is where SBI calls come in for v0.2 and above (like Arm's PSCI)
<jrtc27> also poweroff/reboot, since it knows the best way for your platform (which you *may* be able to do from S-mode, but isn't guaranteed)
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<LetoThe2nd> heh thanks, I'm very much aware of the fact that given enough effort almost anything is possible, or enough caveats to cope with. I just lacked the kind of ecosystem perspective, about whats common.
<conchuod> palmer: as promised
<conchuod> and one last one from me that's fairly recent but is reviewed /shrug https://lore.kernel.org/linux-riscv/20220803185359.942928-1-mail@conchuod.ie/
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<palmer> conchuod: thanks, I'm getting some test failures post-merge but hopefully I'll have time to take more stuff soon
<conchuod> Something in that trigger it or prior palmer
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* conchuod figures you mean in torvalds/master
<conchuod> Unrelated entirely, but I have seen code that works /fine/ in gcc crash on boot for me with clang
<conchuod> But that's not upstream code yet so /shrug
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