sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<mixotricha> Hi. I am building an L-Machine board for a bit of vintage hardware. Somebody else is building an FPGA board that is coming down the pipe line. Will be T35 with about a gig of ram. What I would like to find is a minimal Riscv64 board that isn't much else but FPGA/Ram/GPIO that is ideally already supported in baremetal by either Spike or Qemu. I see
<mixotricha> the LoFive gets close but it is 32 bit.
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<drewfustini> mithro: very exciting!
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<gorgonical> question for the sifive people here: when setting up the timer at the os level, what's the idiomatic way to discover the core frequency? checking corepll on the prci?
<conchuod> palmer: for those riscv{clint,plic} entries in robher's mail - I assume what makes sense is adding them as "deprecated" in the kernel's bindings?
<conchuod> riscv,{clint,plic}0 are in the respective drivers (and the plic one is explicitly marked "for legacy systems" there)
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<conchuod> Also, question for anyone - there's a "u" extension?
<gorgonical> the user extension?
<gorgonical> Last I heard it was retracted
<conchuod> It's not a legal extension is it
<gorgonical> That's my understanding
<gorgonical> That was dh` who told me
<conchuod> Ahh looks like a certain someone tried to drop them a long time ago haha
<conchuod> (there's more than one commit talking about getting rid of the u extension - get it is still being put into my dt!)
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