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<dramforever>
the jh7100 is pinmux whack
<dramforever>
*the jh7100 pinmux is whack
<dramforever>
though iirc at least on both the beaglev starlight and visionfive v1, if you're after 'secondBoot' you can pretty much just ignore the 'global mux' and the per-pin mux behind is okay
<dramforever>
but then, like, all pinmux are like this....
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<dramforever>
courmisch: 'b' is not a real extension, at least not yet
<dramforever>
IIRC current SiFive cores that implement 'B' actually only have Zba_Zbb
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<courmisch>
hmm but the extension is ratified, is it not?
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<dramforever>
Zb{a,b,c,s} are ratified, 'B' isn't
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<dramforever>
I'm expecting a silicon errata from StarFive/SiFive for mistakenly claiming that it supports the nonexistent 'B' extension, otherwise, at least to me, this is just blatant noncompliance
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<courmisch>
strange. is there a plan to more Zbfoo??
<courmisch>
also makes the HWCAP lack of Z* support more pressing
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<dramforever>
there was a lot more in Zb* but they were mostly sort of 'weird'
<dramforever>
check out the 0.93 version
<dramforever>
there are a bunch of generalizations of bit shuffling stuff like grev and gorc, bit matrix operations, some (imho a bit questionable complexity-wise) ternary operations
<dramforever>
and i think 'they' decided that they'd pick out some obviously useful subsets first to ratify
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<jrtc27>
starfive say rv64gc on their kickstarter page...
<jrtc27>
but yes, sifive are misleading on their own u74 page
<jrtc27>
the u74 manual at least says rv64gc_zba_zbb_sscofpmf these days
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<dramforever>
To clarify, since I haven't got the hardware I might be mistaken, but from information I got from a friend who got a beta hardware of some sort, on the VisionFive 2's U74 cores misa.B is 1
<dramforever>
which is, just wrong
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<dramforever>
s/VisionFive 2/JH7110/
<dramforever>
on the other hand though, could zba_zbb have been what got the jh7100 a significantly better benchmark score?
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<dramforever>
oops i mean jh7110
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* hodapp
twiddles thumbs and stares at his Allwinner D1
<jrtc27>
misa isn't visible outside of M-mode anyway and doesn't handle Z*/S*, it's basically useless
<dramforever>
that's true, we just need to get the fdt to say something like riscv,isa = "rv64imafdc_zba_zbb_sscofpmf"
<dramforever>
but comparing it with other sifive docs it does seem to indicate support for zba_zbb
<dramforever>
just looked again, their dt included in the itb actually says riscv,isa = "rv64imafdcbsux"; *facepalm* hope they're working on fixing it
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<jrtc27>
x has never been a valid extension...
<jrtc27>
s and u haven't really but people at least liked to think they were
<jrtc27>
but x...
<jrtc27>
x what?..
<cousteau>
...maybe it's x followed by an empty string?
<cousteau>
RV32GC_Xhwacha_Xds9k_X_Xternary
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<conchuod>
only X I have seen so far is a ventana thing
<conchuod>
and that was only in some qemu patches I think
<conchuod>
and obv. that was _xventanafoo
<conchuod>
not a raw x
<jrtc27>
yes, that's my point
<jrtc27>
xfoo is fine
<jrtc27>
a lone x is like a lone z
<jrtc27>
it makes no sense
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<conchuod>
Ye, was agreeing w/ you
<conchuod>
rv64imafdcbsux looks like a joke with that last 3..
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