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<Sofia>
sorear: load-bearing NOPs?
<Sofia>
dh`: There are various properties I'll try to prove for my compiler. Maybe confluence will be one. If not, I might add a debug warning if it ever finds an example where it doesn't hold.
<Sofia>
jimwilson: Predicted alu instruction..?
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<Sofia>
Re macro-op fusions. Are addi-mul chains emulating "muli" ever fused? I have not seen this mentioned in any documents describing fusions.
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<Sofia>
If `sll rd rs1 [123]; add rd rd rs2` is fused, would the cost of adding `sll rd rs1 [123]; sub rd rd rs2` be negligible in hardware costs? When implemented, are these limited to the 1-2-3 as hot for addressing or are they more general? I'd expect the shifts to be sufficiently cheap to just fuse more generally.
<Sofia>
At least the bitmanip extension provides sh[123]add, which mostly makes the fusion obsolete if limited to 1-2-3. Only mostly because it is "cheaper" to "hope" the fusion applies than "know" the bitmanip extension is present (and active).
<Sofia>
slli*
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<jimwilson>
predicated or conditional, e.g. a branch around a move instruction becomes a conditional move
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<sorear>
Sofia: nobody (publicly) does any of this yet so one could only speculate
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