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<muurkha>
Bluefoxicy: 1/∛3 and pi/fs are both constants, right? I don't see where the 1/sin is in that formula
<muurkha>
oh, that's a ÷! not a +
<muurkha>
can you make a table of (4K sin(f₀π/fs)))³ for each f₀?
<muurkha>
for csc⁻¹ you can approximate it as dh` says, maybe with a cubic spline rather than a series. I'm not sure if there's a way to do csc with CORDIC
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<sorear>
never changes
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<jrtc27>
so how many generation ahead are the press releases with what you can actually get your hands on?
<jrtc27>
three?
<jrtc27>
(8-series, P550, P650, I believe)
<muurkha>
heh
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<sorear>
remember the old jokes about how intel suffered a misprediction and serious pipeline stall after the NetBurst flop
<jrtc27>
based on my experience with riscv hardware so far I'll have to have hands-on experience of the chip's performance before I believe it...
<sorear>
fyi the p550 manual on sifive.com/documentation has a pipeline diagram and a list of performance counters (3.11.4), if you want a rough idea of where they're playing
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<jrtc27>
"Bare and Sv48 virtual memory support"
* jrtc27
hopes they also mean Sv39, because otherwise that's not legal
<jrtc27>
presumably they do given linux only uses sv39...
<jrtc27>
"The BTB has a one-cycle latency, so that correctly predicted branches and direct jumps result in no penalty, provided the target is 16-byte aligned"
<jrtc27>
seems rather restrictive...
<jrtc27>
"For RV64 architectures on SiFive designs, satp.MODE=8 is used for Sv48 virtual addressing, and no other modes are currently supported."
<jrtc27>
uhhhhhhh
<jrtc27>
that's very not legal
<jrtc27>
(to quote the privileged spec, "Implementations that support Sv48 must also support Sv39.")
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<jimwilson_>
p550 is what they used to call u8, there is no u8 anymore
<jrtc27>
ohh ok that clears thing up a bit
<sorear>
Is p2** U7? looks similar
<jrtc27>
yes, see B.1
<jrtc27>
although, having E and S use the same marchid sounds like a bad idea...
<jrtc27>
p270 seems to be a beefed up version
<jrtc27>
has B, Zfh, L3 cache
<jimwilson_>
yes p2** is U7, the second number is base 2 alu size, so p550 has 64-bit alu and p270 has 256-bit alu for V
<jrtc27>
so presumably newer core rtl glued to newer uncore rtl
<sorear>
if bullet is set up like rocket there's just a useVM boolean. probably the same one
<sorear>
if that's going to change marchid then what else should?
* sorear
hopes but doubts they have fun internal train names for p5 and p6
<jimwilson_>
or maybe it is 128-bit alu with 256 bit registers, I don't remember, but registers are twice the size of alu for widening operations
<sorear>
(it was called "bullet" in the gcc pipeline description)
<gudenau[m]>
Isn't there a device tree that gets mapped into memory that you are supposed to parse to get hardware info? I don't know anything about that.
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