<pabs3>
pierce: maybe something like nvidia's use of RISCV? control cores in their GPUs IIRC
pehaef has joined #riscv
pehaef has quit [Client Quit]
pehaef has joined #riscv
<sorear>
it happens periodically, there are a lot more invisible cores than the ones in the GPU
pehaef has quit [Quit: leaving]
elastic_dog has quit [Ping timeout: 268 seconds]
___nick___ has joined #riscv
aburgess_ has joined #riscv
___nick___ has quit [Client Quit]
___nick___ has joined #riscv
elastic_dog has joined #riscv
<pierce>
<pabs3> "Pierce: maybe something like..." <- It mentions both CPUs and micro(controller)s which would mean more than what NVIDIA is currently doing
Sofia has quit [Remote host closed the connection]
Sofia has joined #riscv
mahmutov has quit [Ping timeout: 256 seconds]
aburgess_ has quit [Ping timeout: 256 seconds]
pecastro has joined #riscv
davidlt has joined #riscv
voltron has joined #riscv
Andre_H has joined #riscv
voltron has quit [Remote host closed the connection]
aburgess_ has joined #riscv
jjido has joined #riscv
kailo has quit [Ping timeout: 256 seconds]
<jjido>
Does Risc-V really feel confident one can achieve desktop-class performance with their design choices? Or is it really a low-power/embedded design?
<mort>
I don't think there's anything in the ISA which would preclude it, from what I've seen you get both the same size in memory and the same number of clock cycles for all the common instruction sequences as something like arm and x64
<mort>
the most serious question I would have is how it deals with the lack of complex addressing modes, but I've been fairly convinced that you can work around that with compressed instructions and macro-op fusion
<mort>
not sure about macro-op fusion, that's a microarchitecture thing and not an ISA thing. I wouldn't be surprised if the big sifive cores implement it if it turns out to be a real advantage
<jjido>
Oh yeah. I suppose the BOOM core has that
<mort>
I'll have to ask a risc-v cpu designer I know if he's doing any macro-op fusion, and if yes, how big of an advantage it is, or if no, if he thinks it would realistically be an advantage or if it's not that relevant
jjido has quit [Quit: My MacBook Air has gone to sleep. ZZZzzz…]
davidlt has joined #riscv
vagrantc has joined #riscv
mahmutov has joined #riscv
<ssb>
neither [some specific] architecture design choices, nor microarchitecture features like macro op fusion are required to have "desktop-class" performance. Performance primarily depends on process technology, microarchitecture and cache size. Existing cores offered by SiFive and others already can be implemented in the "desktop class"
<sorear>
mu, none of "desktop-class" "low-power" "embedded" were ever design goals
* sorear
waits for return
<mort>
well, simplicity was a design goal, which is pretty important for embedded and low-power
<sorear>
reaching within a few percent of the commercial state of the art was also a design goal, because the research risc-v was supposed to enable would have been meaningless otherwise
<mort>
then I suppose I don't understand why it matters that those 3 things weren't design goals
<sorear>
because it reflects the speakers narrow-minded approach to a world where the only reasons you would design a CPU would be to either make STM clones or steal Intel's monopoly position
<gudenau[m]>
AMD couldn't even though they where kicking Intel to the curb the last few years. I wouldn't expect RV to get anywhere close. Might be good for an AARCH64 replacement at some point in a couple decades though.
<mort>
but... "Can a risc-v CPU scale up to compete against Intel/AMD/Apple's high end" is certainly a worthwhile question to ask and try to answer, no?
<mort>
I don't know which speaker you're talking about anyways
<sorear>
a risc-v CPU can scale up to be a viable desktop option, at most one or two years behind due to the "design decisions", but "compete" implies additional economic factors
<sorear>
it was a reply to jjido and I was hoping to hold the elaboration until they rejoined
<gudenau[m]>
I'm sure they can scale, AMD64 is so complex for the performance we have get from it.
<gudenau[m]>
That is the big issue with IRC.
<mort>
jjido didn't mention competing, jjido asked if one can achieve similar performance using rv given the design choices
<mort>
I basically interpret that as, "are the design choices in rv which poises major challenges for scaling up a core?"
<mort>
to which I agree the answer is no, but the question is valid
Narrat has joined #riscv
jacklsw has quit [Quit: Back to the real life]
jjido has joined #riscv
<sorear>
my personal unscientific biases are closer to "there are design choices which impose a permanent ~5% penalty for the best core you can design on a given process"
cousteau has joined #riscv
adjtm has quit [Quit: Leaving]
aburgess_ has quit [Ping timeout: 252 seconds]
Narrat has quit [Ping timeout: 252 seconds]
crabbedhaloablut has quit [Remote host closed the connection]
crabbedhaloablut has joined #riscv
jjido has quit [Quit: My MacBook Air has gone to sleep. ZZZzzz…]
EchelonX has joined #riscv
<jimwilson>
sifive cores do macro op fusion to combine a branch around a simple alu instruction to turn it into a conditional/predicated alu operation, this really helps coremark performance which is important in the embedded market
<jimwilson>
this only works for a branch around a single instruction
crabbedhaloablut has quit [Ping timeout: 276 seconds]
jjido has joined #riscv
freakazoid343 has joined #riscv
Narrat has joined #riscv
freakazoid12345 has quit [Ping timeout: 252 seconds]
crabbedhaloablut has joined #riscv
BOKALDO has quit [Quit: Leaving]
<cousteau>
jimwilson: they do? which sifive cores? I thought they were mostly based on rocket
<jimwilson>
cousteau, the unmatched has it, the unleashed does not
<jimwilson>
the 3/5 cores are based on rocket, but have been modified by sifive to add stuff
<cousteau>
oh I see
<cousteau>
that's nice
<jimwilson>
the 7/p2*/x2* and the p5* and p6^ cores are sifive designed, not based on rocket
<cousteau>
I guess this is one aspect in which ARM shines? I recall that one of its main features was that all instructions were conditionally executed
<cousteau>
is the modification open source?
<jimwilson>
some of the early stuff was open sourced, but nothing is open sourced anymore
<jimwilson>
some early stuff for rocket I mean
<sorear>
the rocket-chip framework and rocket proper still have active development, rocket landed the H extension in the last couple months
<jimwilson>
yes, but that stuff isn't coming from SiFive
<sorear>
arm A32 has a 4-bit predicate field in every instruction, although for some system-register and SIMD instructions it can have nonstandard effects