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<Sofia>
Do any processors do "dependent instruction fusing"? Ex. b := slli a imm; c := addi b imm. If yes, do they require the reuse of registers b = c to eliminate the obsolete register write or do they use multiple writebacks?
<Sofia>
I'm primarily interested in current (and potential for future) RISC-V implementations. However I ask generally.
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<sorear>
power10 has some recommended fusion pairs, there are also some in various arm impls
<sorear>
in general, not architectural
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<Sofia>
Xark, sorear: Thanks. Looks like the jumps and post-indexed load need to write to multiple registers.
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<Sofia>
And as expected, most of these macro op fusions (the term I forgot the name..) immediately hide the intermediate value with register reuse.
<Sofia>
If macro-op fusion occurs, does this count as "issuing two instructions" or just one in terms of ports? Ex. if we have a 6-issue core and do mulh-mul, does this consume 1 or 2 of the 6-issue?
<dh`>
if it happens in the decoder it'll be one
<dh`>
which is kind of the point afaik
<Sofia>
As expected. Okay.
<Sofia>
So I kinda had another detail here I wanted. Umm
<Sofia>
When the decoder issues a fused operation, can the decoder still keep up to issue the full 6 instructions or is it a bottleneck?
<Sofia>
Or to rephrase towards the real objective. Does it suffice to know the max-issue, number of ports, distribution of operations per port, and which operations are fused; or do we also need to model more decoder details?
<Sofia>
If a pair of operations are fused, does this ever reduce the set of ports available? I.e. Port#1 supports fusing but Port#2 does not.
<sorear>
you need to model more decoder details.
<Sofia>
Fun.
<Sofia>
Is there a list of microarchitectural choices (and implications) a core can make, which an optimizing compiler would need to know?
<Sofia>
Is it correct to consider jumps (modulo branch prediction) to flush and align the 6-issue per cycle to the jump target and limit out-of-order-ness to this window? Or can out-of-order see further ahead?
<Sofia>
Thanks for the link.
<sorear>
out-of-orderness can see further ahead than jumps, that's the entire point
<sorear>
the compiler can do scheduling within a basic block
<sorear>
there's an entire set of dispatch queues between frontend and issue, generally, and no alignment is maintained
<sorear>
decoding can be influenced by alignment, if you have fun decode properties (like Alpha's one-cycle decode penalty per CMOV in an aligned 16-byte group of instructions)
<Sofia>
Okay. I'll go with sufficiently complex as to ignore for a long time. Hehe.
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<la_mettrie>
platformio seems to think that mtimecmp register is a label... undefined reference to `mtimecmp'
<la_mettrie>
plain assembler has no problems assembling it
<Sofia>
sorear: My cost function plan is to start with a coarse class of implementations ranging from ideal yet impossible to trivial. Setting the lower bound to unbounded decode and issue (dependency graph depth), and upper bound to single issue. Use this partial order to discard all expressions unconditionally worse. Then incrementally tighten the specification for each degree of freedom (ex. removing
<Sofia>
extensions, fusions, or decreasing the vector width), and discard all expressions unconditionally worse for each reduction of the specification.
<Sofia>
In other words: I'd like to render the N-dimensional pareto surface of program performance to hardware implementation choices.
<Sofia>
To guide hardware-software co-design or find the cheapest core to meet a user's budgets for their program.
<Sofia>
I'll start with only the extensions, fusions and vector width (and other small mostly binary choices).
<dh`>
there's a good chance you'll find that your relaxations aren't confluent
<Sofia>
Then move on to compression-friendly register allocation, towards size and fusion-friendliness.
<Sofia>
dh`: Hm?
<Sofia>
Er, I meant in the tightening case that we **partition** the expressions. Not discard.
<Sofia>
This should ensure confluence, no?
<Sofia>
Partition as in: if we remove the B extension, we cannot use the instructions. But if we have B, then emulating them manually is obsolete.
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<Sofia>
dh`: If there is any confluence issue, I will eventually find an example. Maybe find a way to fix it.
<muurkha>
probably the best-known macro-op fusion is in the amd64 family, which nowadays fuse test-jump pairs
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<sorear>
Sofia: the scheduling models llvm and gcc use are horribly simplified, but a majority of users seem to not complain, maybe look at those for inspiration
<sorear>
they really don't know about load-bearing NOPs though
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<geist>
muurkha: yeah some of the newer arm64 cores also explicitly mention macro op for cmp/branch pairs as well
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<dh`>
sofia: sorry, fell asleep
<dh`>
anyway yeah, that should be ok
<dh`>
but the other thing is: at some level if that sort of thing isn't confluent it's a problem with the architecture
<dh`>
it's just that such problems are very hard to detect until you step in them
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<jimwilson>
Sofia, the SiFive u740 in Unmatched can fuse a branch around an alu instruction into a predicated alu instruction, this is supported in gcc for conditional move instructions, more recent cores support more fusion pairs but I don't know what they are