sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
<q66> it's a new project https://chimera-linux.org
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<drmpeg> Cool.
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<pierce> <jimwilson_> "A dual-core C910 board for..." <- Do you have any plans for one of these Jim?
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<stikonas> does anybody know what's the reasoning behind Linux kernel not zeroing registers when risc-v program starts? All other arches seem to be doing that e.g. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/include/asm/elf.h?h=v5.15-rc5#n159
<stikonas> wouldn't this result in data leak from the kernel on execve?
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<jrtc27> that's not zeroing all registers, that's zeroing a single register
<jrtc27> also that comment looks copy-pasted from another arch...
<jrtc27> arm64 does not have a register called a1
<jrtc27> they're all xN, and in this case it's x0
<la_mettrie> openbsd 7.0 adds riscv64 support https://marc.info/?l=openbsd-announce&m=163422237101753&w=2
<jrtc27> that's the register m68k uses though
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<jimwilson> pierce, I'll probably get one to experiment with, the Nezha is too slow to be very useful.
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<jimwilson> old linux kernels had a bug that prevented FP regs from being initialized, that was a data leak between user processes, but I believe that has been fixed, otherwise I'm not aware of any leak
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