sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<dh`> more basically: it has to truncate the value to 32 bits and this is normally done in the callee
<dh`> (for values smaller than int, it has to be, because of the C promotion rules, but that doesn't apply here)
<dh`> (so I wonder if this was ever explicitly decided by anyone or appeared in the compiler by default)
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<jrtc27> specifically "When passed in registers or on the stack, integer scalars narrower than XLEN bits are widened according to the sign of their type up to 32 bits, then sign-extended to XLEN bits." in the calling convention spec
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<muurkha> ohhh. so it's not *garbage* as such it's worried about but *sign-extension*
<muurkha> thanks jimwilson_, dh`, and jrtc27!
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<dh`> ah
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<geist> Question for those that have their finger on the riscv specs and the direction it’s going: do you think W and/or WX page protections (no R) has a future in a future spec? It seems to still be considered reserved
<geist> I kinda doubt it, but it hasn’t bee reclaimed for any other purpose in the spec yet
<dh`> there ought to be only four states, - R RW and RX :-)
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<geist> X is useful in some cases too
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<kaddkaka[m]> How does RISC-V define signed integer division `INT_MIN/-1` ?
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<sorear> "7.2 Division Operations" "Signed division overflow occurs only when the most-negative integer is divided by −1. The quotient of a signed division with overflow is equal to the dividend, and the remainder is zero."
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