sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<somlo> on a (64-bit) Rocket Chip, how can one tell which memory regions support Arithmetic/Logic atomic operations? During elaboration, I get something like this:
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<somlo> Generated Address Map
<somlo> 3000 - 4000 ARWX error-device@3000
<somlo> 2000000 - 2010000 ARW clint@2000000
<somlo> 0 - 1000 ARWX debug-controller@0
<somlo> 10000 - 20000 R X rom@10000
<somlo> c000000 - 10000000 ARW interrupt-controller@c000000
<somlo> 10000000 - 80000000 RWX mmio-port-axi4@10000000
<somlo> 80000000 - 100000000 RWXC memory@80000000
<somlo> RWX are easy, C is "cached" (by the internal L1); not sure what 'A' stands for, but from empirical observation it appears that `memory` supports atomics, whereas `mmio` does not, and the only difference is that `memory` is cached, which isn't an obvious (to me) reason for the difference...