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<geist>
oh hey just got a notice from Intel about the new NIOS V processor they have. you can guess what ISA its based on
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<solrize>
what was nios again?
<solrize>
oh right softcore
<solrize>
maybe they can put some riscv hard macros onto their fpgas
<solrize>
i mean why softcores?
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<drmpeg>
It's only RV32IA.
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<solrize>
yeah what i mean is practical fpgas are full of hard blocks that would be silly to implement as LUTs. e.g. memory, multipliers, etc. why not small cpu cores?
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<muurkha>
I thought the V spec was the whole strategy
<muurkha>
is it more accurate to say a la AArch64 SVE rather than a la Cray?
<zz>
that's what people thought of MMX. And look, we now have SSE4 and beyond.
<zz>
("the whole strategy")
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<jrtc27>
P and V have both been reserved for Packed SIMD and Vectors respectively for years in the unpriv spec
<jrtc27>
with the non-normative text "Discussions at the 5th RISC-V workshop indicated a desire to drop this packed-SIMD proposal for floating-point registers in favor of standardizing on the V extension for large floating-point SIMD operations. However, there was interest in packed-SIMD fixed-point operations for use in the integer registers of small RISC-V implementations. A task group is working to define the new P extension."
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