<muurkha>
organizedglobals: I didn't see your full message
<muurkha>
but people normally use verilog simulators (or VHDL simulators, or SystemC compilers) for that
freakazoid343 has quit [Ping timeout: 258 seconds]
<muurkha>
the next step beyond doing verilog (VHDL, etc.) simulation in software is doing it on an FPGA
<muurkha>
which is fast and cheap enough that sometimes it's how people actually deploy in the field
<muurkha>
but even if your goal is an ASIC, simulating on an FPGA can be useful for debugging
<muurkha>
is that what you were asking about?
freakazoid343 has joined #riscv
freakazoid12345 has quit [Ping timeout: 260 seconds]
<mort>
honestly, I'm pretty sure you can do higher performance simulations in minecraft than with logisim
<mort>
a guy I know is working on a reimplementation of the minecraft server software specifically to be able to run circuits quickly, it's written in rust and actually insanely fast, with plans for even further optimizations in the future
aburgess has quit [Ping timeout: 260 seconds]
<organizedglobals>
any plans for minetest?
elastic_dog has quit [Ping timeout: 264 seconds]
X-Scale` has joined #riscv
X-Scale has quit [Ping timeout: 260 seconds]
X-Scale` is now known as X-Scale
freakazoid12345 has joined #riscv
freakazoid343 has quit [Ping timeout: 258 seconds]
elastic_dog has joined #riscv
rvalles has quit [Ping timeout: 260 seconds]
rvalles has joined #riscv
rvalles has quit [Client Quit]
rvalles has joined #riscv
___nick___ has joined #riscv
<dh`>
question: what's the proper citation for the risc-v SAIL model?
___nick___ has quit [Client Quit]
___nick___ has joined #riscv
mahmutov has joined #riscv
jacklsw has quit [Quit: Back to the real life]
hexteex has quit [Quit: Leaving]
gdd has quit [Remote host closed the connection]
gdd has joined #riscv
jimwilson_ has joined #riscv
jimwilson_ has quit [Quit: Leaving]
jimwilson_ has joined #riscv
jimwilson has quit [Quit: Leaving]
freakazoid12345 has quit [Read error: Connection reset by peer]
freakazoid12345 has quit [Read error: Connection reset by peer]
freakazoid12345 has joined #riscv
haise01 has joined #riscv
freakazoid343 has joined #riscv
freakazoid12345 has quit [Ping timeout: 260 seconds]
BOKALDO has quit [Quit: Leaving]
vagrantc has quit [Quit: leaving]
Peter1 has joined #riscv
Peter1 has quit [Quit: Quit]
Peter1 has joined #riscv
Peter1 has quit [Client Quit]
Peter1 has joined #riscv
Peter1 has quit [Client Quit]
shicz has quit [Ping timeout: 260 seconds]
shicz has joined #riscv
Andre_H has joined #riscv
X-Scale has quit [Ping timeout: 245 seconds]
X-Scale` has joined #riscv
X-Scale` is now known as X-Scale
<mort>
organizedglobals: no plans for minetest
EchelonX has quit [Quit: Leaving]
smartin has quit [Quit: smartin]
___nick___ has quit [Ping timeout: 260 seconds]
grubman9000 has quit [Remote host closed the connection]
freakazoid12345 has joined #riscv
freakazoid343 has quit [Ping timeout: 258 seconds]
adjtm_ has quit [Quit: Leaving]
winterflaw has quit [Ping timeout: 276 seconds]
cwebber has quit [Ping timeout: 258 seconds]
zjason has quit [Read error: Connection reset by peer]
zjason has joined #riscv
compscipunk has quit [Quit: WeeChat 3.3]
compscipunk has joined #riscv
mahmutov has quit [Ping timeout: 260 seconds]
grubman9001 has joined #riscv
anyone has joined #riscv
<anyone>
A function like uint64_t f(uint32_t x) { return (uint64_t)x << 1; } produces {slli a5,a0,0x20; srli a0,a5,0x1f;} under gcc. Is there a reason it couldn't just do {slli a0,a0,1;}?
aburgess has joined #riscv
adjtm has joined #riscv
adjtm_ has joined #riscv
mort has quit [Quit: Ping timeout (120 seconds)]
mort has joined #riscv
adjtm has quit [Ping timeout: 260 seconds]
<muurkha>
anyone: interesting, it's like it's worried the high bits of a0 are full of garbage
Andre_H has quit [Ping timeout: 260 seconds]
freakazoid12345 has quit [Read error: Connection reset by peer]
freakazoid12345 has joined #riscv
<GenTooMan>
that sounds the most likely reason although technically speaking the best method would be to mask it then shift, the assumption the compiler is making is that a barrel shifter is in the processor, which is not always the case.
[itchyjunk] has joined #riscv
adjtm has joined #riscv
adjtm_ has quit [Ping timeout: 260 seconds]
<anyone>
maybe it's the linux ELF sysvabi - clang emits the same (slli/srli)
pecastro has quit [Ping timeout: 260 seconds]
<jimwilson_>
a 32-bit value is always sign-extended to 64-bits, even if unsigned, that is an ISA requirement, so converting a unsigned 32-bit value to unsigned 64-bit requires a zero-extend, there is no zero extend instruction (before zba/zbb), so we need a pair of shifts, the optimizer then combines that shift pair with a following shift left, so that we have 2 shift total instead of 3