sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<mort> risc-v is very neat
<mort> https://p.mort.coffee/niw.mp4 I implemented rv32i in logisim, thought some people here might enjoi
<mort> enjoy*
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<muurkha> awesome mort! :)
<mort> https://github.com/mortie/rv32i-logisim-cpu here it is, in case anyone feels like playing around with it
<mort> still a WiP, I haven't implemented half-word and byte stores and loads, and you can't read from the ROM with load instructions
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<muurkha> this is super sweet. is the narration missing or is my audio just broken?
<mort> nah, it's just a quick video I recorded to show it off, no narration or anything
<muurkha> ah cool
<muurkha> I've never used logisim, it looks better than I'd imagined
<mort> that's the CPU itself
<mort> I love how radically simple and regular risc-v is
<mort> the only thing I found weird is how the ALU operation changes based on whether you're in register-register or register-immediate; you have a sub instruction with register-register, and that's selected by choosing the add operation with funct3 and setting bit 30 to 1
<muurkha> it's awesome
<mort> I think I would instead give add and sub separate alu ops, and then combine all the shifts under a single op which uses, say, bit 29 and bit 30, to select between sll, srl and sra
<mort> just to let the alu operation be encoded the same in both register-register and register-immediate
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<GenTooMan> mort did you use logisim-evolution for that?
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<mort> I did
<mort> I don't think there's anything evolution-specific there though
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