<Xav101>
I'm trying to write a linker script to place sections in memory and I'm not quite sure what to do with the global pointer register
<Xav101>
For example often you'll have an LMA and a VMA for data section because it resides in ROM and then gets copied into RAM
<Xav101>
from what I understand you're supposed to set the gp to the center of that most used 4k area of data so it can do relative jumps easily or whatever
<Xav101>
but do I set it to the center of that location in RAM or in ROM? And if it's in RAM what's the best way to do that with a linker script
<jrtc27>
symbols will take the VMA, the LMA just affects the program headers
<jrtc27>
and gp isn't used for jumps
<jrtc27>
it's used for loads/stores
<jrtc27>
normally you'd just put __global_pointer$ = . + 0x800; at the start of a section
<jrtc27>
(the default has it doing that for .sdata)
<geist>
Xav101: it's a bit of a question when it comes to a split RAM/ROM region like that
<geist>
since you can't really cover both. I put it near the ram version of it, since the rom version can still compute relative addresses to the .text segment *fairly* easily
<geist>
or, just reclaim the gp register in a split world and do something else with it
<jrtc27>
that doesn't quite work, there's no way to turn it off in bfd without disabling linker relaxation entirely
<geist>
that's what i mean
<jrtc27>
you can give it an address in the linker script that's never going to be in range of something
<jrtc27>
but that doesn't disable it and is a bit gross
<geist>
just disable relaxation entirely and/or don't set the __global_pointer$ symbol and it never uses it
<geist>
but yeah, YMMV
<jrtc27>
there are lots of relaxations you *do* want
<geist>
fair, eah
<Xav101>
I mean relaxation of jumps is quite helpful
<jrtc27>
like not having two instruction indirect(ish, without fusion) branches to all your functions
<geist>
but i did leave myself a comment about what to do with .srodata
<geist>
which gets 'left behind' in the ROM segment
<geist>
oh or actually doesn't, but could be. that's the comment
<geist>
i think i found in a limited amount of testing that the compiler doesn't really generate much in the way or .srodata as much as it likes to genera .sdata and .sbss
<geist>
but honestly i found the whole sdata/gp thing to be kinda annoying, since it's hard to have it automatically do what you want, its just a best effort thing and based on whatever the linker did when it laid out things you may or may not get what you want in the small data area
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<Xav101>
@geist can you explain how that linker script puts it in the RAM portion? The script doesn't seem to have much of a "RAM portion"
<geist>
this is for an embedded riscv machine, where you have say ROM around 0 and RAM at 0x2000.0000 or so
<geist>
externally the build system splits the two and the linker script builds two output segments here
<geist>
the real trick is the AT() keyword in line 55
<Xav101>
right, so AT makes it so the data is in ROM but stored in RAM?
<Xav101>
*stored in ROM but should be loaded into RAM
<geist>
line 53 shifted the virtual address the linker is generating up to the base of RAM but the AT() keyword keeps the addresses physically rooted at the original run, which is in ROM
<geist>
right
<Xav101>
ah, so when you set GP it's set to a value in RAM
<geist>
it sets up some symbols like __data_start_rom and __data_start that some assembly code uses to memcpy the RAM portions out
<geist>
right
<Xav101>
ok
<Xav101>
I'll have to try that with my linker script
<geist>
there's probably other ways to do it, linker scripts are kinda a black art, but this has worked well for me
<Xav101>
I don't know if any of you guys have played factorio
<Xav101>
but I ended up building what seems like a functional RISC-V CPU in it with the in-game logic system
<Xav101>
so now I'm just asking about this stuff to see if I can get it to run C code
<geist>
heh i have and i learned to stay far away from it. haha
<geist>
omg that's awesome
<geist>
probably at least a bit more reliable than building cpus out of redstone in minecraft
<Xav101>
lol. Also faster. I think theoretically I could hit 10Hz if I rebuilt the design with some tight timing constraints and a pipeline
<geist>
yah i wouldn't worry too much about the GP register then
<Xav101>
well I mean the linker relaxation does help slightly with code size
<Xav101>
just cause you don't need to double up all your jumps
<geist>
that is true though
<Xav101>
I'm struggling for RAM pretty badly.
<geist>
but it probably wont use the gp register for jumps though
<geist>
unless the code is so small it happens to also have some pieces of text within the gp register range
<geist>
and you have some indirect jumps
<Xav101>
yeah but even if you have linker relaxation on then doesn't it still need it
<geist>
gp register stuff is mostly for referencing data, global registers, etc. AFAICT the relaxation is the linker will simply use GP as a base if the target label is within the offset range of it
<geist>
as opposed to storing the full address (for non pic) or using the PC to compute t
<Xav101>
so how would I turn off the relaxation so it doesn't need the reg but still can relax jumps?
<geist>
s/global registers/global variables
<geist>
i think if you simply dont put in the __global_pointer$ label in your linker script the linker will simply never emit any code
<geist>
but can still relax other stuff
<Xav101>
ok
<geist>
simply never emit any code to use GP that is. the mechanism is quite simple and the linker doesn't really know much
<geist>
but i'm not too familiar with the other relaxations other than GP referencing, jrtc27 can probably answer better
<xentrac>
is there a way you can publish your CPU design so other factorio players can try running it?
<Xav101>
yeah probably when I've got this all done and maybe debugged it a bit
<xentrac>
historically speaking RAM was a huge problem for a long time
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<xentrac>
from about 01945 to about 01955 (and up to 01965 in cost-sensitive applications) people used delay lines, magnetic drums, and Williams tubes, so they could have thousands of bits of RAM without thousands of separate physical devices to store the bits in. I haven't played Factorio so I don't know if there's a similar thing you can do in it
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<Xav101>
@xentrac yeah there sort of is? There's some weird stuff you can do but you'll lose speed, and halfword and byte stores are already bad enough with my current design so I'm not going to deal with that just yet.
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<stefanct>
jimwilson: thanks, that's a bit hidden (not mention in the getting started or reference manual. it's very odd though that they are not included but 4 screws + 4 washers (half of which are completely useless AFAICT)
<stefanct>
i "fixed" it with some m3 screws and two nuts
<stefanct>
(but then recognized - despite the m.2 slot keying - the sata lines are not connected and there is no sata controller in the soc ;)
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<mps>
anyone runinng riscv64 in qemu VM with u-boot as boot loader
<Xav101>
@jrtc27 I'm trying to do a thing where the data section is placed in ROM but is loaded into RAM. To define the start and end points for where to copy the data into RAM from I was going to define some symbols using the location counter and then la them so I know where to start/stop
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<jrtc27>
IMO you want a section with your data whose VMA is in RAM and LMA is in ROM, with start and end symbols
<jrtc27>
then add a single symbol that is the address of the start of the data in ROM
<jrtc27>
you then have all the information you need, and that's most compatible with ELFs
<jrtc27>
so they bought MIPS to make CPUs, failed, sold MIPS, MIPS stopped being MIPS and started making RISC-V cores and now Imagination are making RISC-V cores too
<jrtc27>
what a mess
<jrtc27>
I wonder if they'll be adopting RISC-V for their GPUs (presumably they have controllers on there like the ones nvidia talk(ed) about replacing with RISC-V microcontrollers?)
<jrtc27>
presumably not so interested in replacing their actual GPU ISAs
<dh`>
at least it's riscv and not say m88k or other bologna
<sorear>
return of m88k would be... interesting
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<dh`>
afaicr there was nothing particularly wrong with it other than 80s microarchitecture
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