<pierce>
<jrtc27> "so they bought MIPS to make CPUs..." <- I'd love it if they went full circle and licenced their RISC-V core from MIPS
<geist>
i860 ftw!
<geist>
you know you can do it intel...
<solrize>
itanium!
<solrize>
iapx432!
<geist>
one of these days i want to get my hands on an actual apx432
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<pierce>
<solrize> "iapx432!" <- I really wanna see this in an FPGA
<pierce>
Just to see "what could have been"
<pierce>
Chuck out the Ada nonsense and supplant it with c# 😜
<sorear>
a new and reasonable implementation of the ISA, or a cycle accurate emulation of the 43201/43202? :P
<sorear>
it's just not the same without 1000-cycle procedure calls
<solrize>
lol
<solrize>
i had the impression the 432 wouldn't have been so horribly slow if they had managed to get it on one die
<solrize>
which was harder back then
<sorear>
the ISA was designed under the assumption a lot of things would be cached but then they discovered they didn't have room for it, so on top of the 16 bit microcode thing it's also spending a huge number of microinstructions fetching and storing things that should be registers
<sorear>
also, the 16 bit microcode bus didn't leave them room for unmultiplexed address/data buses out of the 43202, so your memory cycles take like 6 bus clocks
<geist>
oh gosh totally forgot it being a two chip solution
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<sorear>
(and this was back when intel was still putting everything in DIPs - I think the pin grid array deserves more credit for late-80s performance improvements than it usually gets)
<solrize>
geist 3 chips iirc
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<sorear>
there were 5 chips, '01 and '02 comprised the cpu, the rest were bus arbiters / RAM interfaces / DMA
<sorear>
3 might have been the minimum for a 1-processor system
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<pierce>
<sorear> "a new and reasonable implementat..." <- ¿Por qué no los dos?
<sorear>
a reasonable fpga implementation would not be cycle accurate
<sorear>
you could of course do two projects
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<solrize>
software simulation probably exists and would certainly beat the pants off the original hardware
<pierce>
<solrize> "itanium!" <- I honestly wanted an itanium to mess around with VLIW/EPIC, see what the fuss is about making a compiler for it is! Surely it can't be that hard!
<pierce>
<solrize> "i had the impression the 432..." <- And yeah, the overall speed
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<pierce>
<solrize> "software simulation probably..." <- I've had a precursory look, but haven't found anything
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<jrtc27>
pierce: I find writing itanium assembly fun
<jrtc27>
the ILP scheduling stuff isn't *that* hard, modern compilers do far more complicated things
<jrtc27>
dealing with the speculative memory accesses is more annoying as it doesn't really fit into existing compiler designs
<jrtc27>
you wouldn't want to model that kind of thing in your IR so would probably have to be a late pass as part of scheduling that does some nasty transformations
<pierce>
honestly, i have no experience writing compilers, but i think the idea of solving a "big computer science problem" like this would go a long way in changing the perception of VLIW and auto-vectorisation
<pierce>
i feel that VLIW is taken seriously, and hasn't been researched enough, and discredited due to it not fitting the traditional compiler paradigms that we see in GCC/LLVM et al
<pierce>
* i feel that VLIW isn't taken seriously, and hasn't been researched enough, and discredited due to it not fitting the traditional compiler paradigms that we see in GCC/LLVM et al
<pierce>
and we're just one discovery away from realising "aha, this is what VLIW is for"
<pierce>
sorry... this is really off topic
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<jimwilson>
speculation does cause trouble, there is a long lasting gcc IA-64 bug where it can sometimes generate reads of uninit regs, and this fails with a trap if the uninit reg has the NaT (not a thing) bit set, but there is no way to convince the gcc optimizer to always init a reg before reading it, https://gcc.gnu.org/bugzilla/show_bug.cgi?id=21111
<jimwilson>
I stopped caring about IA-64 before I figured out how to fix this
<xentrac>
oh that? that's not a thing
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<dh`>
nothing's stopping you from writing a compiler for itanic :-)
<dh`>
and I would say that the primary problem with VLIW at this point is instruction bandwidth, not compiler-level scheduling
<pierce>
Honestly I'm likely going to spend my time getting .net on RISC-V
<pierce>
I know I'm late to the party, but I'm hoping I can weigh in on the J SIG too
<pierce>
So much to learn, so much to do, it's almost overwhelming!
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<mps>
managed to boot riscv kernel in qemu with u-boot and got this https://tpaste.us/BgWW
<mps>
and it stays till I kill it
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<mps>
rebuilding kernel with some options and drivers change and it now boots fine