sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<seds> does qemu implement only the interger extension?
<seds> nevermind, found the on the documentation: https://qemu.readthedocs.io/en/latest/system/target-riscv.html
<geist> which extension do you mean? it implements at least *gc
<geist> ie, mafdc
<jrtc27> IMAFDCBVH currently
<jrtc27> with B V and H not yet ratified so could change
<geist> it is all fairly current though, so if you have a particularly old qemu it may be one of the first implementations
<geist> jrtc27: huh! didn't notice the BVH stuff, i'll have to fiddle with
<seds> geist: yeah, I thought qemu implemented only igc by default, but I just found out it also supports a few boards too
<geist> yah but note that G == MAFD
<sorear> G = IMAFD
<sorear> "ig" is redundant
<jrtc27> ig is illegal :)
<seds> oh right
<sorear> (there's also the Zicsr stuff now)
<geist> fine. but anyway, point is the 'g' holds FD
<jrtc27> yeah most pretend Zicsr doesn't exist and is just I..
<geist> 'i' is kinda redundant IMO, but it is what it is
<jrtc27> no
<sorear> I means not E
<jrtc27> e exists
<geist> floating point only cpu!
<geist> aaaah, okay, retract then. forgot about e
<jrtc27> you could argue it's redundant for rv64 though as there is no rv64e
<jrtc27> but, consistency
<geist> worst part of irc is i can't edit typos
<geist> or slips
<geist> there's lots of good about irc, not knocking it, but kinda getting used to line editing in newer stuff...
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<dh`> letters for extensions was never going to be workable even if a couple important things hadn't been forgotten up front
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<solrize> does anyone not implement C? in big processors it's small enough that you can chuck it in, and in small processors you need it since you're likely to be short of code space
<palmer> solrize: it's been a while since I've seen any production-ASIC-track cores that lack C, but it's not nearly as common for some of the edge cases -- mostly research/academic stuff, but I've also seen reasonable arguments for not having C in some soft cores (as the cost models there can be quite different than when targeting an ASIC)
<solrize> yeah softcores sure, but if it's a softcore then it's fine to implement a subset and tweak your compiler if that's what floats your boat
<solrize> what about E where they eliminate half the registers? does anyone use that?
<solrize> seems kind of unfortunate to not reclaim the encoding bits
<palmer> I'd actually argue the other way: if you can afford to run stuff on a soft core then you probably don't care that much about the performance of that workload, so you likely don't want to drag along a custom toolchain
<palmer> E is super common
<solrize> hm ok
<palmer> the E cores are just usually the ones you don't see: they're deeply embedded things that end users aren't even told about, much less program
<solrize> didn't realize that riscv had gotten into so many places already
<palmer> IMO that's the most common use case for RISC-V, it's certainly the only one I see in production today
<solrize> i guess western digital is putting them into hdd controllers
<solrize> maybe they're using E for that
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<jimwilson> the Indian Shakti processor is linux capable and doesn't have C, though they may add it in a later version, I walked one of those guys through the process of building a cross native toolchain, so he could get a native linux compiler that didn't emit C by default, they are trying to build their own C less linux distro
<jimwilson> nvidia is considered the first to ship RISC-V cores, they have been shipping video cards with RISC-V cores on them for several years now, but they aren't user visible cores
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<pierce> What are the advantages of having a "C-less" core?
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<sorear> it's conceptually simpler because you have one size of instructions, an instruction is never split between cache lines or pages, you don't need to treat *epc and *tval separately in instruction page faults, a superscalar fetch line of (say) 16 bytes always consists of exactly 4 instructions, etc
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<sorear> none of this translates into a significant amount of _gates_ but it does add design time, which is at a premium if you're working on a research project
<sorear> also, getting rid of C means you now have over 3/4 of the 32 bit instruction space free - lots of room to add whatever you're doing research on
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<jimwilson> I think the issue with Shakti was just miscommunication. They didn't realize that everyone else had decided to adopt C by default.
<sorear> it was also their first chip, if someone told me that they were planning to add C but it wasn't high priority I would believe it
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<xentrac> sorear: I feel like all that stuff translates to a significant amount of gates if you're doing a really tiny core
<xentrac> although as solrize points out if you're paying for CPU transistors and RAM transistors out of the same budget, -C is probably a win