sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<pierce> how do i find out what the benefits are to using the "-mcpu=sifive-u74" compiler flag?
<pierce> https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html doesn't really tell me much
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<palmer> pierce: how specific are you looking for? at a high level it just generates code in a way the U74 likes. There's a bunch of normal stuff (it's a dual issue in order core), and there's also some tricks the front end can play (for short branches)
<pierce> nothing too specific, i think you've answered it for me. i just wanted ti know if it was actually doing much compared to the vanilla compile
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<jrtc27> it will also imply the exact -march= string if not already supplied
<jrtc27> whereas -mtune= will solely guide its optimisation choices
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<pierce> <jrtc27> "it will also imply the exact -..." <- Yeah that's what the gcc docs say
<pierce> But I saw a comment thread for a pull request on llvm saying that there was some discrepancy there
<pierce> Mind you, I skimmed over it and I'm not sure if it's fixed or not
<jrtc27> I don't recall
<jrtc27> I was just going off how I know it works for AArch64 with Clang
<jrtc27> (which I think is the right model)
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<pierce> Apparently there's also inconsistent behaviour between x86 and arm too!
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<geist> pierce: looks like in gcc at least you generally get slightly different tunings, as palmer pointed out
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