<bslsk05>
www.righto.com: The Pentium contains a complicated circuit to multiply by three
<nikolar>
whoop new righto article dropped
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<klys>
if you could have a toy to demo a triode, perhaps as an inverter with a button and a flashy light, would you like that
<klys>
by triode I mean four-pin vacuum tube
<klys>
some logic could of course be used to regulate the voltages and prevent shorts
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<zid>
heat
<heat>
zid
<zid>
I wrote an OS again
<heat>
congrats
<zid>
don't
<zid>
I want support
<heat>
wat
<zid>
"Omg that's so tragic, is there anything I can do for you?"
<heat>
lol
<zid>
I wrote a bunch of acpi code so I could get at the madt to get all my lapid IDs, went to look at the IPI docs and there's just.. a "everybody but me" mode I can use? :/
<zid>
lapic*
<zid>
then they can cpuid to find their own id when they wake up
<zid>
I am hurt
<heat>
you're not supposed to use that mode
<zid>
stop me
<heat>
IPI broadcast ignores offlined CPUs and because of that everyone just does a point-to-point IPI
<zid>
they're not offline according to the docs, they're ONLINE
<zid>
just not.. started? it's weird
<zid>
there's a bit flag 0 that says online or offline, and if they're offline, can they be onlined, and they're all online
<heat>
yes those flag semantics are weird
<zid>
why no broadcast
<zid>
oh there's one idea
<heat>
because if e.g the BIOS disables a few CPUs the broadcast will wake those up too
<zid>
maybe there are CPUs that the bios detected as bad
<zid>
yea
<zid>
and then didn't put those into the MP/madt
<zid>
I should be avoiding them
<heat>
AIUI you'll see them in the MADT, but with !enabled && !online_capable flags
<zid>
yea
<zid>
so yea, I have my lapic list, I just shoved them into a struct cpu { int lapic_id; } cpus[MAX_CPUS]; for now, I'll walk it later and wake them up.. then I read I needed a 10ms delay, so I think I need to do idt first, and then figure out lapic timer
<zid>
THEN I can online
<heat>
yeeeeep
<zid>
I liked the idea of
<zid>
128 way ipi broadcast to wake up a herd of cpus
<zid>
and have them all madly dash to some random cs:ip to try escape
<zid>
like when a new xpac in wow launches and everyone wants to get ahead on the quest lines
<zid>
so they're not fighting for mob spawns
<zid>
"no, *I'M* taking the blk so I can allocate myself a stack *punch*"
<heat>
some chipsets have been so fucked such that even bringing up APs (with point-to-point IPIs) in parallel is risku
<zid>
bkl*
<zid>
ah well, if they're fucked they can fuck off, ez
<zid>
oh you can put a PAGE NUMBER in cs? That sounds fun, fill ram with a bunch of mov esp, n*4096
<zid>
and have them all start on a different one
<heat>
lol christ
<zid>
wait wait
<zid>
lock xadd [stack], 4096
<heat>
for practical reasons that does not work
<zid>
128 cpus all executing the same lock xadd sounds *fun* though
<heat>
that's what a certain polish guy would say is PESSIMAL
<zid>
can't be worse than linux
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<heat>
but hey could be worse, could be ll/sc
<zid>
they spend 100ms calibrating rtdsc and 10ms loading microcode and shit
<zid>
according to this random patch from 2023 I found to try clean some of this stuff up
<zid>
palralralell bringup patches cus CLOUD IDIOTS were complaining
<zid>
that their 128 virtual core webserver machines took forever to boot
<zid>
when they're trying to start/stop 4000 vms a second
<bslsk05>
github.com: Onyx/kernel/arch/x86_64/realmode.S at master · heatd/Onyx · GitHub
<heat>
i copy all of that shit into the start page
<zid>
no cheating
<heat>
(which i also pick as 0)
<zid>
they can cpuid their lapic and just index an array for all I care
<zid>
lapic id*
<zid>
but I'd need a reverse lookup for lapic id
<zid>
ur phys base is weird
<heat>
yeah that can also work but then you need to be careful if you care about doing timeouts and retries and shit
<zid>
mine is 0xffff8 urs is 0xffffd
<heat>
if you're wondering, the rest of the code (startup_secondary_32) is in boot.S
<zid>
nope
<heat>
it's a bit of a mess but also, kind of the same x86 stuff you always do
<zid>
I wanna for(int i = 0; i < maxcpus; i++) send_init_ipi(i); sleep(10ms); for(int i = 0; i < maxcpus; i++) if(!cpus[i].online) printf("This guy eating beans");
<zid>
not start them all individually
<zid>
so I like the idea of THUNDERING HERDing them, or even doing code_page = lapic_id;
<heat>
code_page = lapic_id doesn't work
<heat>
memory down there is super tight
<heat>
plus you max out at lapic 0xff
<heat>
anything over goes boom i'd assume
<zid>
how big are the page, 4k? then I guess 640/4k = max out at lapic id = 160
<heat>
oh how cute, assuming the 640k conventional memory area is there :v
<zid>
I mean, it is, on real machines
<zid>
have you considered having one of those
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<heat>
sorry i only use efi
<zid>
and it has reserved it, it's still there
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<zid>
try reclaiming it all
<zid>
000VV000H, where VV is the vector contained in the SIPI message
<zid>
so yea, 4k
<zid>
lol
<zid>
intel's step 5 for "What to do if you're an AP being initialized"
<zid>
Executes the CPUID instruction with a value of 0H in the EAX register, then reads the EBX, ECX, and EDX registers to determine if the AP is “GenuineIntel.”
<heat>
yes, what other x86 vendor is there?
<heat>
x86 is not big and extensible like riscv
<zid>
not going to work on my machine :(
<heat>
anyway ping me once you get rcu
<zid>
I have one of those already
<zid>
really crap uptime
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* kof673
squints, blinks........so that's a thing.........
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<Ermine>
seems like clangd can't stand C++ in .h headers
<nikolar>
as it shouldn't
<nikolar>
int class;
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<Ermine>
not a lot of people use .hpp suffix for c++ headers
<nortti>
I've seen .hh
<nikolar>
Ermine: can't you override it
<nikolar>
tell it that it's hpp
<Ermine>
nortti: you can probably see .cc in those projects
<Ermine>
nikolar: actually i can
<nikolar>
there we go
<Ermine>
thx
<nikolar>
lol you're welcome
<heat>
clangd can stand C++ in .h if it realizes it's compiling it in C++ mode
<heat>
usually with a bunch of heuristics wrt what TUs include that header
<zid>
-x cpp should b e nanned
<zid>
also be banned
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<nikolar>
zid: int class!
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<nikolar>
should we just add that to all headers
<zid>
I mean, if you're running headers through a compiler directly, you already have your own problems to deal with in life
<nikolar>
i mean true
<nikolar>
but this is clangd
<zid>
cringed
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<kof673>
re: c++ and headers............is .h .c .cpp .hpp .hh simply convention or actually "standardized" anywhere? i might as well use .nasal_daemon .deathstar_3000 file extension it is true "standard headers" is a standard concept...but the contents of a "header" ? e.g. inline functions, code...is there anything in any "standard" saying a "header" must only have declarations and not definitions?
<kof673>
if there is no standard, anything goes..............
<kof673>
"anything not locked down will be stolen"
<heat>
convention
<kof673>
stdio.h for C i assume is in the standard, but maybe that is just shorthand and not even required :D
<kof673>
that is the preprocessor i guess....
<kof673>
meaning, i believe C at least has ".h file" as part of "standards"
<kof673>
semi-related too, more practical....can headers have compiler-specific extensions or not, are they required to e.g. have a define to only allow standard things in the header, so that other tools can parse them without toolchain-specific extensions
<kof673>
gcc extensions, ms vc, whatever...........this is sometimes a real problem for a cross-compiler if the headers are using things only a different compiler supports
<kof673>
i bet the answer is "anything goes"....just saying, where are the contents of system headers in this case, fully standardized? they must provide some function declaration or type or define, other than that...........
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<Jari-->
I forgot this
<Jari-->
what configuration does qemu take to use the host IP, e.g. to run a web server
<Jari-->
I guess thats bridged?
<zid>
heat
<zid>
lapic, its address is FEE0xxxx by default, do you carve that out from your allocator near boot, or do you just move the lapic
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<zid>
oh I have AN HOLE there
<zid>
*ignores the issue for now*
<zid>
*ignores PAT too*
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<kof673>
qemu has tap stuff quoth the qemu.org docs: Using TAP network interfaces . This is the standard way to connect QEMU to a real network
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<kof673>
"standard" of course means host-specific
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<demindiro>
Assembly is surprisingly endearing. It makes some things more difficult but the control it gives you over stack and register usage allows neat tricks.
<demindiro>
And also no fuzzing with types or UB or other stuff like that, just bits & bbytes.
<demindiro>
I also think I'm going to redesign my scripting language (again) since the core alone is already 1200 lines, which I probably won't be able to reduce and is already over my target for "minimal" and approaching the limit for "simple"
<demindiro>
Maybe I should model it more like a form of assembly...
<GeDaMo>
Have you considered Forth?
<demindiro>
It's something that has been on my TODO list for a while
<demindiro>
I should put my mind to that first
<demindiro>
AFAIK Forth doesn't really have a concept of "immutable everything" though, which I consider critical
<demindiro>
(at least structures passed around as values, the outside world is mutable of course. Not much I can do about that)
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<nortti>
you may find other concatenative languages like factor useful to look at, then
<geist>
one thing i also point out sometimes at work is with assembly once you write it it stays that way forever. short of an assembler somehow picking up a bug, it'll not assemble any other way
<geist>
vs having to deal with compilers deciding to restructure your stuff. for better or worse
<nortti>
there are cases where different assemblers might choose differently, in case of multiple possible encodings of an instruction or when handling pseudoinstructions like loads of immediates
<kof673>
1200 lines of what? </rhetorical>
<kof673>
3d game engine, just 20 lines of JS
<nortti>
actually, how do risc-v linker relaxations interact with assembly? I presume you'll need to mark yourself where you want them to be applicable
<demindiro>
x64 assembly
<geist>
nortti: they dont. basically the assembler always emits the long form of the instruction and the linker is allowed to reduce it to a smaller one
<geist>
to accomplish this the assembler also spits out a bunch of extra relocations that assist with relaxation
<geist>
basically every point where relaxing an instruction would cause other ones to need to be tweaked (short branches that now need to be smaller, etc)
<geist>
well okay they do interact in that regard
<geist>
the assembler leaves enough context for the linker to do its work
<nikolar>
oh geist is here
<nikolar>
hello geist
<geist>
hiya!
<geist>
i've been quiet lately but still read along
<geist>
mostly just busy and dealing with house shit (tree fell on my house, etc)
<nikolar>
oh i hope that gets resolved
<geist>
yep, just dealing with contractors and insurance. only real risk is getting rain in the house in the interim
<geist>
but it's patched up enough now that it should be okay
<nikolar>
i hope your pdps and vaxen are safe :)
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<heat>
zid, yeah if firmware didn't carve that out it's broken
<zid>
I added the UC bit to that mapping too in the page table, but I haven't checked the little PAT table to see if that means what it should
<heat>
carve that out or even add it in the first place, usually that high fourth gb is never wired with any memory but PCI and chipset shit, as you may know
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<zid>
yea, I figured that's where my pci-e and shit are too, cus I have a lot missing
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<geist>
oh hey hackernews picked up on fuchsia again
<geist>
happens every once in a while
<heat>
hey at least it doesn't look negative
<geist>
it's fresh, not enough time yet for the trolls to come out
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