_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<acathla> I do a clk48 = plat.request("clk48"), is there a simple way to get the pin number of that signal?
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<somlo> 4.8 seconds to read a 14.7M file from disk, 9 seconds to write a similarly sized file to disk: https://pastebin.com/f05kQ3Ri
<tpb> Title: ...[ 0.959684] Unpacking initramfs...[ 1.231110] LiteX SoC Controller - Pastebin.com (at pastebin.com)
<somlo> next is adding IRQ support (probably after another week or two of $DAYJOB imposed delays... :)