06:54 <tnt> Mmm, AFAICT there is no way in migen to generate the `ramstyle=”ultra”` needed on a Memory to get the tool to infer ultra ram blocks.

07:20 <_florent_> tnt: I'll do a test with 512-bit on the XCU1525 design

07:22 <_florent_> tnt: The verilog/memory generation is now directly integrated in LiteX; I haven't tried to used UltraRAM yet with LiteX. Can you share some expected verilog code to infer them? I could try to add this

16:07 <_florent_> somlo: I just added IRQ/Identify support to LiteSATA gateware and the BIOS is now running the Identify command during SATA init to get disk information

16:07 <_florent_> somlo: https://github.com/enjoy-digital/litex/commit/1d20bbcd01784158088e1eb85e219309cfce0248

16:15 <somlo> _florent_: awesome, I'm building it right now and will test it as soon as it's finished

16:16 <somlo> I'll be traveling starting tomorrow until Monday, so no opportunity to tinker with the linux driver, but I should hopefully have some time to add write, irq, and identify (really just set the device size) support sometime starting next week

16:17 <somlo> oh and partition detection when the device is successfully probed -- seems to be another layer on top of just having a raw block/disk :)

16:20 <_florent_> somlo: no hurry, I just wanted to implement it to avoid blocking you (and to remove it from my todo list :))

16:24 <somlo> I saw the work you did earlier (before the bios identify example) and had already started building it, with the intention of studying the identify python stuff in litesata later on

16:25 <somlo> so it's nice to have a "color by numbers" example already implemented, saves me from having to learn *too* many new things ;)

18:05 <pepijndevos[m]> hmmm so how do I synthesize VHDL with Litex? It tries to use yosys with read_vhdl. Does that require verific? Can I make it use GHDL?

18:15 <pepijndevos[m]> pffffff https://github.com/enjoy-digital/litex/blob/1d20bbcd01784158088e1eb85e219309cfce0248/litex/soc/cores/cpu/microwatt/core.py#L218-L232