02:36 <Hammdist> I will go with VexRiscv for now

02:42 <Hammdist> can VexRiscv run from FPGA BRAM, without external memory? (assuming the firmware is small and fits on there)?

04:19 <jevinskie[m]> Yes

04:34 <xobs[m]> We do that with foboot, where we actually fit the firmware into an 8 kb rom that's in the bitstream.

07:02 <swetland> Is there a recipe for using multiple LiteEth + PHY instances?

07:03 <swetland> I can name the phys (eth0, eth1) and macs (ethmac0, ethmac1), but things are not happy about collisions in the clock domains

09:01 <acathla_> I plugged a 48MHz oscillator to pin 35 of a iCE40up5k-SG48i FPGA, was it a mistake? I don't understand why nextpnr is not happy with it. I tried calling icepll with primitive="SB_PLL40_PAD". Is it because I use the 48MHz is used for POR?

09:08 <tnt> You can't use the clock for anything else than feeding the PLL.

09:09 <acathla> So there is still no litex-way to do that yet?

09:09 <tnt> Of doing what ?

09:11 <acathla> Using the 48MHz for power on reset. How do I build a POR if the PLL is reset and feeds a counter...

09:12 <tnt> Nothing to do with litex, it's the ice40 architecture that doesn't let you use the clock signal for anything else than feeding the PLL.

09:13 <tnt> This is how I made the CRG for instance https://github.com/no2fpga/no2migen/blob/master/examples/1bitsquared_icebreaker_bitsy_usb.py#L39

09:13 <tnt> POR is on the PLL output side and driven by the lock signal from the PLL.

09:14 <tnt> On power on the lock will be low and only rise once the pll has stabilized and its output it good. At that point the por counter will start decrementing and at some point release the system reset.

09:17 <acathla> tnt, ok, perfect, thank you!