_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
tpb has quit [Remote host closed the connection]
tpb has joined #litex
toshywoshy has quit [Ping timeout: 252 seconds]
toshywoshy has joined #litex
Degi_ has joined #litex
Degi has quit [Ping timeout: 252 seconds]
Degi_ is now known as Degi
<_florent_> swetland: might be of interest: https://twitter.com/enjoy_digital/status/1403259359518396418
<_florent_> the modification is really easy to do
<swetland> florent: I actually have a couple of those around somewhere. Also I'm having JLCPCB fab me a few of these: https://twitter.com/dnaltews/status/1526225492583403523
<swetland> thanks for the pointers!
<swetland> perhaps unsurprisingly mine already is modified: http://frotz.net/misc/phy-module.jpg
cr1901 has joined #litex
TMM_ has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
TMM_ has joined #litex
<pepijndevos[m]> is ResetSignal active high? https://m-labs.hk/migen/manual/reference.html#migen.fhdl.structure.ResetSignal
<tpb> Title: API reference — Migen 0.8.dev0 documentation (at m-labs.hk)
<tnt> yes
<pepijndevos[m]> ty
FabM has joined #litex
FabM has joined #litex
SpaceCoaster_ has joined #litex
Moe_Icenowy has joined #litex
guan_ has joined #litex
LoveMHz_ has joined #litex
mithro_ has joined #litex
pavelow_ has joined #litex
tedh_ has joined #litex
mlaga97_ has joined #litex
shorne_ has joined #litex
shoragan_ has joined #litex
mlaga97 has quit [*.net *.split]
xobs[m] has quit [*.net *.split]
a3f has quit [*.net *.split]
mikolajw has quit [*.net *.split]
pepijndevos[m] has quit [*.net *.split]
shoragan[m] has quit [*.net *.split]
CarlFK has quit [*.net *.split]
Crofton[m] has quit [*.net *.split]
shorne has quit [*.net *.split]
shoragan has quit [*.net *.split]
tedh has quit [*.net *.split]
SpaceCoaster has quit [*.net *.split]
guan has quit [*.net *.split]
mithro has quit [*.net *.split]
MoeIcenowy has quit [*.net *.split]
LoveMHz has quit [*.net *.split]
pavelow has quit [*.net *.split]
LoveMHz_ is now known as LoveMHz
SpaceCoaster_ is now known as SpaceCoaster
guan_ is now known as guan
mithro_ is now known as mithro
Finde_ has joined #litex
Finde has quit [Read error: Connection reset by peer]
xobs[m] has joined #litex
pepijndevos[m] has joined #litex
Crofton[m] has joined #litex
shoragan[m] has joined #litex
a3f has joined #litex
CarlFK has joined #litex
mikolajw has joined #litex
FabM has quit [Quit: Leaving]
Finde_ is now known as Finde
mlaga97_ has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
mlaga97 has joined #litex
cr1901_ has joined #litex
cr1901 has quit [Ping timeout: 248 seconds]
peeps[zen] has joined #litex
peepsalot has quit [Ping timeout: 248 seconds]
Melkhior has quit [Remote host closed the connection]
Melkhior has joined #litex
swetland has quit [Quit: Connection closed for inactivity]
Guest2675 has joined #litex
cr1901_ is now known as cr1901
<tnt> _florent_: Can I just set data_width to 512 to the PCIe PHY ? Or does it need other changes ?
<tnt> Because turns out with sys_clk of 200 MHz, 256b is "only" 51.2Gb/s (vs 64 Gb/s theoritical)
Guest2675 has quit [Quit: Client closed]
<_florent_> tnt: this should do it yes, I just checked the xcu1525 bench and data_width is only passed to the PHY
<tnt> _florent_: definitely doesn't work :) Crashes the host for me.
<tnt> (on modprobe)
<jevinskie[m]> _florent_: I’ve looked at the 7 series PHYs in litedram and when looking to port to max10 I realized they only have dedicated serdes on the lvds bank not the ram banks. Guess I’ll have to implement that in logic?
<jevinskie[m]> And I think the max10 programmable delays are fairly limited in range/precision and are fixed at synthesis time
shoragan_ has quit [Quit: quit]
shoragan has joined #litex
cr1901_ has joined #litex
cr1901 has quit [Read error: Connection reset by peer]
cr1901 has joined #litex
cr1901_ has quit [Ping timeout: 240 seconds]