<zmatt>
dinuxbg: just in case I've tested the sub+suc and sub+adc combinations against real hardware using py-uio: https://pastebin.com/X7Ka37Q5
<zmatt>
so I don't know why I thought pru had an inverted meaning for the carry flag... the way it works is actually perfectly reasonable
<zmatt>
*for the carry-flag when used with sub/suc
<zmatt>
or at least it's how I'm used to add/sub-with-carry to work
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<zmatt>
dinuxbg: actually, it looks like your pru simulator misimplements sub/suc ?
<zmatt>
(in a way that causes incorrect results when passing carry from add/adc to sub/suc or vice versa)
<zmatt>
ahhh so THAT's how the idea got into my head
<zmatt>
I did in fact at some point consult your pru.isa file, that's probably how I started thinking pru treated it as a borrow-flag
<zmatt>
dinuxbg: of course there is an oddity here: the ARM-style use of carry as "not borrow" stems from fact that this makes sbc( a, b, carry_in ) equivalent to adc( a, ~b, carry_in ) so in hardware that just means conditionally inverting the second argument depending on whether it's add or subtract (and that same conditional invert is also used to turn "and" into "bic" on ARM)
<zmatt>
but this gets a bit funky for PRU with its ability to use 8- and 16-bit register fields as operands
<zmatt>
if all operands are 16-bit then there's no problem except "~b" is a 16-bit invert
<zmatt>
but pru allows b to be 32-bit even if the sub/suc has a 16-bit destination, which you need to compute (a + (b ^ 0xffff) + carry_in) to get the correct result in bits 0..15 and correct carry_out in bit 16
<zmatt>
in the end of course it's the same as what you're doing except you need to invert the carry_in and carry_out for sub and suc
<zmatt>
(and doing so is definitely more readable then what I just wrote above ;)
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