00:42 <_whitenotifier> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±2] https://github.com/YoWASP/yosys/compare/3a460cce84b4...5843bbebdf4f

00:42 <_whitenotifier> [YoWASP/yosys] whitequark 5843bbe - Update dependencies.

04:35 <_whitenotifier> [amaranth-boards] cr1901 commented on pull request #214: Add MachXO2 Breakout board - https://github.com/amaranth-lang/amaranth-boards/pull/214#issuecomment-1694156831

13:17 <sporniket> Hello, back to toying a little with amaranth hdl after a long period toying with other thing ; bumping my dependencies, I notice the warning about the deprecation "DeprecationWarning: instead of using `Past`, create a register explicitly"

13:17 <sporniket> The thing is

13:18 <sporniket> I don't know at all what I should write instead.

13:19 <sporniket> I searched a little bit for an hint (some issues about Past like #526,

13:19 <sporniket> googling this libera chat salon's history about "Past"

13:20 <sporniket> looking at amaranth.hdl.ast.py for clues

13:20 <sporniket> )

13:20 <sporniket> but I admit that I have no idea

13:20 <sporniket> of what to do

13:23 <sporniket> So, what would be the equivalent of "Past(dut.mysignal, n_cycles_back_in_time)" given I have just a single clock ?

13:24 <sporniket> thanks in advance

13:26 <jn> sporniket: as far as i understand it: creating a register explicitly more or less means creating a shift register which is shifted by 1 on every clock, and always gets the current value of your signal on the input end. then, you can access shiftreg[n] to get the value that is n cycles in the past

13:26 <jn> (i haven't tried it myself so i can't provide exact syntax for this)

13:31 <sporniket> ha, that I understand better, I can work from that.

13:31 <sporniket> thanks

18:49 <galibert[m]> If you have two identical Case() in a switch, even on an enum, there's no warning

18:49 <galibert[m]> (it's not two complex matches which happen to have a common values subset, it's pure equality)