<galibert[m]>
Is there a sane way to have a theoretically 8 bits register but which is actually 6 and bits 4 and 5 are wired to 1? Just to be sure they don't end up with storage defined for the extra bits?
<galibert[m]>
or two bits is just too little to care?
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<jfng[m]>
if it mattered, i'd make a wrapper which would only store 6 bits, and drive an output equal to Cat(storage[:4], Const(0b11, 2) storage[4:])
<galibert[m]>
yeah, I guess. Some derivatives use more bits... so I guess I'm going to go for the "too little" case
<galibert[m]>
(6502 flag register)
<vipqualitypost[m>
maybe you could also just do that with comb logic? just to set 4/5 eq bit 1?
<vipqualitypost[m>
although, then you end up with mixed domains for the register which seems like a mess.
<vipqualitypost[m>
(if it would even work)
<jfng[m]>
driving parts of a Signal from different domains is an error in amaranth
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<cr1901>
galibert[m]: nextpnr automatically will collapse constants "1" and "0" to use only a LUT (all entries set to "1" or "0" and driven by the default inputs to the LUT, which will be either a valid 1 or 0) and not a FF. I assume Quartus does something similar.
<cr1901>
So it'll use the minimum amount of resources required
<cr1901>
The above should be suffixed with "if you use jfng[m]'s solution*"