<crzwdjk>
How does one communicate the right clock constraint from amaranth down to nextpnr? Right now I set up a PLL but nextpnr is still assuming the default frequency of 12 MHz which is not actually correct.
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<whitequark[cis]>
platform.add_clock_constraint()
<crzwdjk>
I recall not being able figuring out the right way to invoke it but I will look again
<crzwdjk>
In particular, I can't seem to use "ClockSignal('sync')" as the first parameter.
<whitequark[cis]>
yes. this is not supported
<whitequark[cis]>
(there is a reason why it cannot be well supported right now)
<whitequark[cis]>
do you have the clock domain for sync around?
<whitequark[cis]>
set the constraint on cd.clk
<crzwdjk>
Aha, that does the trick, thanks. I don't remember why I didn't think to try that.
<whitequark[cis]>
it's not obvious and I don't fault you for not figuring it out
<crzwdjk>
The whole clock domain thing is pretty subtle. Also in my earlier attempt at this project it all somehow worked anyway, I am not sure by what magic.
<whitequark[cis]>
it's not only subtle but also has a number of design flaws...
<galibert[m]>
I’ve done a rfc with some proposals to make clock domains (I think) better, but it will be post 0.4 at a minimum
<galibert[m]>
Ah too bad, the orange crab is sold out, I guess they're overwhelmed with the glasgow at this point
<whitequark[cis]>
it's available from farnell
<galibert[m]>
Ah nice
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<bob_twinkles[m]>
(did 1bit2 ever do assembly for the OC?)
<gatecat>
think greg always arranged the assembly of it himsekf
<gatecat>
*himself
<galibert[m]>
that would get me an ecp5, the glasgow will get me a ice40, so the main missing one will be xilinx (fuck they're expensive) and I guess things like gowin and whatever else? I'm trying to see if I can cover everything nextpnr handles
<gatecat>
~~some of our fabulous mpw2 samples~~
<galibert[m]>
mpw2?
<gatecat>
there was a test tapeout on mpw2 of the fabulous efpga generator, and we can build designs for that with nextpnr
<galibert[m]>
oh. Yeah, well, yeah
<galibert[m]>
(I didn't match multi-purpose wafer immediatly :-) )
<whitequark[cis]>
glasgow isn't a good devboard
<whitequark[cis]>
sure you can run arbitrary bitstreams on it, but then you're on your own
<galibert[m]>
Hey, it's a devboard I can plug things on while reducing the risk of blowing it off
<galibert[m]>
It's not exclusive. It's not because I run my bitstreams from time to time that I can't ever use your magnificient system too
<galibert[m]>
there's no "rooting" crap or whatever, you wouldn't do that
<galibert[m]>
and it has a bunch of very usable i/os have five cute leds, what else does one could want?
<galibert[m]>
s/have/and/
<galibert[m]>
plus schematics, documentation, good toolchain support...
<whitequark[cis]>
it's not about my system being magnificent, it's more about it getting in your way
<whitequark[cis]>
since you'll have to keep it tethered via usb at the moment
<galibert[m]>
I'll see, scheduled for next year anyway
<jer_emy[m]>
AliExpress has some decent Xilinx 7 series boards
<jer_emy[m]>
Looks for “qmtech”
<galibert[m]>
nice to know
<galibert[m]>
yeah, they look interesting
<jer_emy[m]>
There is also “icesugar” if you want an ice40up5k and “colorlight” if you want a super cheap ecp5-25f
<jer_emy[m]>
The store “muse lab” also has some decently priced lattice boards
<josuah>
and plenty of Pmod boards that are not Digilent-priced :)
<whitequark[cis]>
colorlight has -45f variants too
<_whitenotifier>
[amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] 7335376 - Deploying to main from @ amaranth-lang/amaranth@f95fe451861066ae7e3ae6c9eb85778de5e949e0 🚀
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<galibert[m]>
Can I have multiple m.Case(...) for the same block?
<whitequark[cis]>
can you show an example?
<galibert[m]>
m.Case(0x02): m.Case(0x04): [something] would be the C-equivalent
<galibert[m]>
* with m.Case(0x02): with m.Case(0x04): [something] would be the C-equivalent
<whitequark[cis]>
with m.Case(0x02, 0x04):
<galibert[m]>
nice, thanks
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