<mcc111[m]>
So I'm looking at how you're allowed to create multiple clock domains, and you can use any signal as the clock for a domain, meaning I could cause an event to trigger on a signal's rising edge by creating a clk_edge="pos" sync domain for that signal. However, I see claimed in several places in the document I'm reading that a value can't be written to by multiple domains. I think this means that if a signal is written from both my
<mcc111[m]>
"rising edge domain" and also from some other domain, that's not allowed. Is that correct? What is the recommended way to do something "on edge" given this limitation?
<crzwdjk>
You can store the previous value of the thing and then compare it to the current value
<crzwdjk>
e.g. m.d.sync += thing_prev.eq(thing)
<crzwdjk>
with m.If(thing != thing_prev): ...
<whitequark[cis]>
mcc111: if you are a beginner, most of your designs should be in one clock domain
<whitequark[cis]>
you can think of having multiple clock domains roughly the same way as having multiple threads
<whitequark[cis]>
there are similar synchronization issues that arise
<whitequark[cis]>
however, on an FPGA, you do not have Thread Sanitizer or anything like that. if you don't get synchronization right, you're mostly just screwed in really opaque ways
<josuah>
for real-world complex ASICs too I suspect, designers try to keep it all under the same clock domain
<josuah>
something like "sysclk", often the same as the central MCU bus
<whitequark[cis]>
'it depends'
<whitequark[cis]>
these days you often just can't afford one clock domain, for various reasons (power is an important one)
<whitequark[cis]>
but the cost is still high
<whitequark[cis]>
even on small MCUs you usually have 3-4 clock domains at least
<whitequark[cis]>
a common one is CPU, APB, AHB
<whitequark[cis]>
and usually something else, like an RTC clock domain, or an analog one, or USB, or something
<whitequark[cis]>
so despite the costs you still see a lot of CDC
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<mcc111[m]>
OK thanks
<mcc111[m]>
<crzwdjk> "You can store the previous value..." <- That makes sense, it seems surprising there isn't a lower level primitive tho, i thought fpga had specific edge detection parts
<adamgreig[m]>
it has lots of things designed to run on clock edges, but it's generally a mistake to run those off arbitrary signals that aren't clock signals