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<twam> Thanks! That looks promising. Do know if there are any examples. Documentation looks a bit sparse 😉
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<Greg> As an overview: you use ecpbram to create an 'init' file that's filled with pseudo-random values. You thin use this to fill the BRAM in your FPGA design. Once you have the .config file out of nextpnr, you run ecpbram again, this time providing it with the original init file, and your actual BRAM contents, it will create a new patched.config file. Which is fed through ecppack to create the final bitstream.
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<Greg> Here are the two lines from some LiteX projects which is doing the same thing you want to do python # Create rand-fill os.system(f"ecpbram --generate {rand_rom} --seed {0} --width {32} --depth {soc.integrated_sram_size // 4}") ### Build gateware, and run Yosys/nextpnr ### Build firmware # Insert Firmware into Gateware os.system(f"ecpbram --input {input_config} --output {output_config} --from {rand_rom} --to {blkram_init}")