01:05 <_whitenotifier-8> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://github.com/YoWASP/yosys/compare/5c808dde5162...d0204876ba6e

01:05 <_whitenotifier-8> [YoWASP/yosys] whitequark d020487 - Update dependencies.

18:45 <roflin> I currently have a Elaboratable which uses another Elaboratable and I'm writing a TestBench for it. All the signals of the inner are connected to the outer signals or internal state of the outer elaboratable, but when I run the TestBench it tells me that the inner Elaboratable is created but never used. I do not drive the signals of the inner Elaboratable itself, but I thought this would be

18:45 <roflin> done by sumulating the outer... Am I supposed to do this differently?

18:46 <whitequark> you need to add the inner one as a submodule

18:47 <roflin> right... I've done this in my top design...

18:47 <roflin> but not in this one :)

18:48 <roflin> Yup that worked, thanks

19:41 <richardeoin> does anyone have advice / pointers on simulating amaranth containing Instances written in verilog?

19:41 <richardeoin> this is a great example of adding verilog sources https://github.com/adamgreig/amaranth-examples/blob/master/amaranth_examples/instance.py

19:41 <richardeoin> my aim is to simulate something like this and get the vcds

19:42 <richardeoin> amaranth with the pysim backend makes simulation so easy that I'm a little lost when I can't rely on it completely

19:42 <whitequark> there's a new backend, cxxsim, in the works that will make this as easy

19:42 <whitequark> but it's not done yet

19:44 <agg> in the meantime, I guess best bet is to dump the amaranth to verilog, combine with the external verilog, and use cxxrtl?

19:44 <agg> or verilator/iverilog/etc I guess

19:45 <whitequark> yes

19:45 <agg> writing test benches in c++ is so much less fun than in python/pysim though :p

19:45 <richardeoin> oh awesome about cxxsim supporting this in future

19:46 <richardeoin> agg: yes that's a reasonable approach

19:47 <richardeoin> I'm also looking at cocotb

19:47 <richardeoin> don't really care about speed here

20:03 <Sarayan> agg: otoh cxxsim is orders of magnitude faster

20:04 <agg> Sarayan: yea.. so I can't wait to write test benches in python and have them run in cxxrtl, cxxsim's going to be great

20:28 <Sarayan> agg: it sure will